Table 2-45. R_Msr_Pmon_Ctl{15-8} Event Select - Intel BX80571E7500 - Core 2 Duo 2.93 GHz Processor Programming Manual

I ® X ® P 7500 S
NTEL EON ROCESSOR
PORT4_IPERF0
PORT4_IPERF1
PORT4_QLX0
PORT4_QLX1
PORT4_XBAR_MM1
PORT4_XBAR_MM2
PORT5_IPERF0
PORT5_IPERF1
PORT5_QLX0
PORT5_QLX1
PORT5_XBAR_MM1
PORT5_XBAR_MM2
PORT6_IPERF0
PORT6_IPERF1
PORT6_QLX0
PORT6_QLX1
PORT6_XBAR_MM1
PORT6_XBAR_MM2
PORT7_IPERF0
PORT7_IPERF1
PORT7_QLX0
PORT7_QLX1
PORT7_XBAR_MM1
PORT7_XBAR_MM2
ILLEGAL
U P G
ERIES NCORE ROGRAMMING

Table 2-45. R_MSR_PMON_CTL{15-8} Event Select

Name Code
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
0x0F
0x10
0x11
0x12
0x13
0x14
0x15
0x16
0x17
0x18-
0x1F
UIDE
Description
Select Event Configured in R_CSR_PORT4_IPERF0
Select Event Configured in R_CSR_PORT4_IPERF1
Select Event Configured in R_CSR_PORT4_QLX_EVENT_CFG[*0]
Select Event Configured in R_CSR_PORT4_QLX_EVENT_CFG[*1]
Set1 Port4 XBAR Mask/Match
Set2 Port4 XBAR Mask/Match
Select Event Configured in R_CSR_PORT5_IPERF0
Select Event Configured in R_CSR_PORT5_IPERF1
Select Event Configured in R_CSR_PORT5_QLX_EVENT_CFG[*0]
Select Event Configured in R_CSR_PORT5_QLX_EVENT_CFG[*1]
Set1 Port5 XBAR Mask/Match
Set2 Port5 XBAR Mask/Match
Select Event Configured in R_CSR_PORT6_IPERF0
Select Event Configured in R_CSR_PORT6_IPERF1
Select Event Configured in R_CSR_PORT6_QLX_EVENT_CFG[*0]
Select Event Configured in R_CSR_PORT6_QLX_EVENT_CFG[*1]
Set1 Port6 XBAR Mask/Match
Set2 Port6 XBAR Mask/Match
Select Event Configured in R_CSR_PORT7_IPERF0
Select Event Configured in R_CSR_PORT7_IPERF1
Select Event Configured in R_CSR_PORT7_QLX_EVENT_CFG[*0]
Select Event Configured in R_CSR_PORT7_QLX_EVENT_CFG[*1]
Set1 Port7 XBAR Mask/Match
Set2 Port7 XBAR Mask/Match
(* illegal selection *)
UNCORE PERFORMANCE MONITORING
2-80