Table 2-80. M_Msr_Pmu_Zdp_Ctl_Fvc Register - Field Definitions; Table 2-81. M_Msr_Pmu_Zdp_Ctl_Fvc.evnt{4-1} Encodings - Intel BX80571E7500 - Core 2 Duo 2.93 GHz Processor Programming Manual

I ® X ® P 7500 S
NTEL EON ROCESSOR
Table 2-80. M_MSR_PMU_ZDP_CTL_FVC Register – Field Definitions
Field
ig
pbox_init_err
evnt3
evnt2
evnt1
evnt0
resp
bcmd
fvid
smi_nb_trig
resp_match
bcmd_match
fast_rst
alrt_frm
psn_txn
mem_ecc_err
smi_crc_err
U P G
ERIES NCORE ROGRAMMING
HW
Bits Reset
Val
31:24 Reads 0; writes ignored.
23 0 Extension of event select encoding 0b111 (smi_nb_trig). If event select
is set to 111 and this bit is set to 1, PBOX reset time events will be
counted.
22:20 0 FVC Subevent 3 selection. See
"M_MSR_PMU_ZDP_CTL_FVC.evnt{4-1} Encodings"
19:17 0 FVC Subevent 2 selection. See
"M_MSR_PMU_ZDP_CTL_FVC.evnt{4-1} Encodings"
16:14 0 FVC Subevent 1 selection. See
"M_MSR_PMU_ZDP_CTL_FVC.evnt{4-1} Encodings"
13:11 0 FVC Subevent 0 selection. See
"M_MSR_PMU_ZDP_CTL_FVC.evnt{4-1} Encodings"
10:8 0 B-Box response to match on. See
"M_MSR_PMU_ZDP_CTL_FVC.RESP Encodings"
7:5 0 B-Box command to match on. See
"M_MSR_PMU_ZDP_CTL_FVC.RESP Encodings"
4:0 0 FVID to match on

Table 2-81. M_MSR_PMU_ZDP_CTL_FVC.evnt{4-1} Encodings

Name Value
0b111
0b110
0b101
0b100
0b011
0b010
0b001
0b000
UIDE
Reset Type
Select Intel SMI Northbound debug event bits from the Intel SMI
status frames as returned from the Intel 7500 Scalable Memory
Buffers OR PBOX init error (see pbox_init_err field). These bits
are denoted NBDE in the Intel SMI spec status frame description.
An OR of all the bits over all the Intel 7500 Scalable Memory
Buffers is selected here as an event.
NB debug events generate multiple triggers for single NBDE
event. Instead, the following triggers listed in
M_CCSR_MSC_TRIG_SEL reg must be used:
Trigger 51: = Ch1 NBDE
Trigger 58 := Ch0 NBDE
Use response match as programmed by
Z_CSR_PMU_ZDP_CTL_FVC.resp to generate trigger.
Use B-Box command match as programmed by
Z_CSR_PMU_ZDP_CTL_FVC.bcmd to generate trigger.
Fast reset request from MBOS
An alert frame was detected.
A write to memory was poisoned.
Memory ECC error detected (that is not a link-level CRC error).
Link level Intel SMI CRC error detected.
UNCORE PERFORMANCE MONITORING
Table 2-81,
Table 2-81,
Table 2-81,
Table 2-81,
Table 2-82,
Table 2-82,
Description
2-108