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I
® X
® P
7500 S
NTEL
EON
ROCESSOR
2.8
W-Box Performance Monitoring
2.8.1
Overview of the W-Box
The W-Box is the primary Power Controller for the Intel Xeon Processor 7500 Series.
2.8.2
W-Box Performance Monitoring Overview
The W-Box supports event monitoring through four 48-bit wide counters (W_MSR_PERF_CNT{3:0}).
Each of these four counters can be programmed to count any W-Box event. The W-Box counters will
increment by a maximum of 1 per cycle.
The W-Box also provides a 48-bit wide fixed counter that increments at the uncore clock frequency.
For information on how to setup a monitoring session, refer to
.
Monitoring Control"
- Umask enables core to scope events for each core (one-hot encoding) (Bit 0 in umask for Core 0, Bit
1 in umask for core 1, etc).
2.8.2.1
W-Box PMU - Overflow, Freeze and Unfreeze
If an overflow is detected from a W-Box performance counter, the overflow bit is set at the box level
(W_MSR_PMON_GLOBAL_STATUS.ov/ov_fixed), and forwarded to the U-Box where it is also captured
(U_MSR_PMON_GLOBAL_STATUS.ov_w).
HW can be also configured (by setting the corresponding .pmi_en to 1) to send a PMI to the U-Box
when an overflow is detected. The U-Box may be configured to freeze all uncore counting and/or send a
PMI to selected cores when it receives this signal.
Once a freeze has occurred, in order to see a new freeze, the overflow field responsible for the freeze,
must be cleared by setting the corresponding bit in W_MSR_PMON_GLOBAL_OVF_CTL.clr_ov/
clr_ov_fixed. Assuming all the counters have been locally enabled (.en bit in data registers meant to
monitor events) and the overflow bit(s) has been cleared, the W-Box is prepared for a new sample
interval. Once the global controls have been re-enabled
Interval from Frozen
Counters"), counting will resume.
U
P
G
ERIES
NCORE
ROGRAMMING
UIDE
UNCORE PERFORMANCE MONITORING
Section 2.1, "Global Performance
(Section 2.1.4, "Enabling a New Sample
2-124
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