S-Box Registers For Mask/Match Facility; Table 2-31. S_Csr_Pmon_Ctr{3-0} Register - Field Definitions; Table 2-32. S_Msr_Mm_Cfg Register - Field Definitions - Intel BX80571E7500 - Core 2 Duo 2.93 GHz Processor Programming Manual

I ® X ® P 7500 S
NTEL EON ROCESSOR
The S-Box performance monitor data registers are 48b wide. A counter overflow occurs when a carry
out bit from bit 47 is detected. Software can force all uncore counting to freeze after N events by
preloading a monitor with a count value of (2
the U-Box. Upon receipt of the PMI, the U-Box will disable counting (
Counter Overflow"). During the interval of time between overflow and global disable, the counter value
will wrap and continue to collect events.
In this way, software can capture the precise number of events that occurred between the time uncore
counting was enabled and when it was disabled (or 'frozen') with minimal skew.
If accessible, software can continuously read the data registers without disabling event collection.
Table 2-31. S_CSR_PMON_CTR{3-0} Register – Field Definitions
Field
event_count
2.5.3.4

S-Box Registers for Mask/Match Facility

In addition to generic event counting, each S-Box provides a MATCH/MASK register pair that allows a
user to filter outgoing packet traffic (system bound) according to the packet Opcode, Message Class,
Response, HNID and Physical Address. Program the selected S-Box counter to capture TO_R_PROG_EV
to capture the filter match as an event.
To use the match/mask facility :
a) Set MM_CFG (see Table 2-32, "S_MSR_MM_CFG Register – Field
b) Program match/mask regs (see
MM_CFG[63] == 1, a write to match/mask will produce a GP fault).
NOTE: The address and the Home Node ID have a mask component in the MASK register. To mask off
other fields (e.g. opcode or message class), set the field to all 0s.
c) Set the counter's control register event select to 0x0 (TO_R_PROG_EV) to capture the mask/match
as a performance event.
d) Set MM_CFG reg bit 63 to 1 to start matching.
Field
mm_en
ig
U P G
ERIES NCORE ROGRAMMING UIDE
- 1) - N and setting the control register to send a PMI to
48
HW
Bits Reset
Val
47:0 0 48-bit performance event counter
Table 2-33, "S_MSR_MATCH Register – Field
Table 2-32. S_MSR_MM_CFG Register – Field Definitions
HW
Bits Reset
Val
63 0 Enable Match/Mask
62:0 Read zero; writes ignored.
UNCORE PERFORMANCE MONITORING
Section 2.1.1.1, "Freezing on
Description
Definitions") reg bit 63 to 0.
Definitions"). (if
Description
2-49