Ubox Performance Monitoring Events; Ubox Box Events Ordered By Code; Ubox Box Performance Monitor Event List; U_Msr_Pmon_Fixed_Ctl Register - Field Definitions - Intel Xeon E5-2600 Series Monitoring Manual

Intel® Xeon® Processor E5-2600 Product Family Uncore Performance Monitoring
Table 2-4. U_MSR_PMON_FIXED_CTL Register – Field Definitions
Field
rsv
en
rsv
rsv
Table 2-5. U_MSR_PMON_FIXED_CTR Register – Field Definitions
Field
rsv
event_count
2.2.4

UBox Performance Monitoring Events

The set of events that can be monitored in the UBox are summarized in Section 2.2.
2.2.5

UBOX Box Events Ordered By Code

The following table summarizes the directly measured UBOX Box events.
Table 2-6. Performance Monitor Events for UBOX
EVENT_MSG
LOCK_CYCLES
2.2.6

UBOX Box Performance Monitor Event List

The section enumerates the uncore performance monitoring events for the UBOX Box.
EVENT_MSG
• Title: VLW Received
• Category: EVENT_MSG Events
• Event Code: 0x42
• Max. Inc/Cyc: 1, Register Restrictions: 0-1
• Definition: Virtual Logical Wire (legacy) message were received from Uncore. Specify the thread
to filter on using NCUPMONCTRLGLCTR.ThreadID.
Reference Number: 327043-001
HW
Bits Attr Rese
t Val
31:23 RV
22 RW
21:20 RV
19:0 RV
Bits Attr Reset
63:44 RV
43:0 RW-V
Event
Symbol Name
Code
0x42
0x44
0 Reserved (?)
0 Enable counter when global enable is set.
0 Reserved. SW must write to 0 for proper operation.
0 Reserved (?)
HW
Val
0 Reserved (?)
0 48-bit performance event counter
Extra Max
Select Ctrs Inc/
Bit Cyc
0 0-1 1
0 0-1 1
Description
Description
Description
VLW Received
IDI Lock/SplitLock Cycles
21