References - Intel BX80571E7500 - Core 2 Duo 2.93 GHz Processor Programming Manual

I ® X ® P 7500 S
NTEL EON ROCESSOR
Box
M-Box 1
M-Box 0
S-Box Counters
S-Box 1
S-Box 0
B-Box Counters
B-Box 1
B-Box 0
U-Box Counters
U-Box
W-Box Counters
W-Box
1.4

References

The following sections provide a breakdown of the performance monitoring capabilities of each box.
• Section 2.1, "Global Performance Monitoring Control"
• Section 2.2, "U-Box Performance Monitoring"
• Section 2.3, "C-Box Performance Monitoring"
• Section 2.4, "B-Box Performance Monitoring"
• Section 2.5, "S-Box Performance Monitoring"
• Section 2.6, "R-Box Performance Monitoring"
• Section 2.7, "M-Box Performance Monitoring"
U P G
ERIES NCORE ROGRAMMING UIDE
Table 1-2. Uncore Performance Monitoring MSRs
MSR Addresses
0xE5E-0xE5C
0xCFB-0xCF0
0xCEB-0xCE4
0xCE2-0xCE0
0xE56-0xE54
0xCBB-0xCB0
0xCAB-0xCA4
0xCA2-0xCA0
0xE5A-0xE58
0xCD7-0xCD0
0xCC3-0xCC0
0xE4A-0xE48
0xC57-0xC50
0xC43-0xC40
0xE4E-0xE4D
0xC77-0xC70
0xC62-0xC60
0xE46-0xE45
0xC37-0xC30
0xC22-0xC20
0xC11-0xC10
0xC02-0xC00
0x395-0x394
0xC97-0xC90
0xC82-0xC80
Description
Match/Mask Registers
Counter/Config Registers
Subconfig Registers (FVC,PLD,PGT,THR,MAP,ISS,DSP)
+ Timestamp Register
Global (Control/Status/Ovf Control)
Match/Mask Registers
Counter/Config Registers
Subconfig Registers (FVC,PLD,PGT,THR,MAP,ISS,DSP)
+ Timestamp Register
Global (Control/Status/Ovf Control)
Match/Mask Registers
Counter/Config Registers
Global (Control/Status/Ovf Control)
Match/Mask Registers
Counter/Config Registers
Global (Control/Status/Ovf Control)
Match/Mask Registers
Counter/Config Registers
Global (Control/Status/Ovf Control)
Match/Mask Registers
Counter/Config Registers
Global (Control/Status/Ovf Control)
Counter/Config Registers
Global (Control/Status/Ovf Control)
Fixed Counter/Config Registers
Counter/Config Registers
Global (Control/Status/Ovf Control)
INTRODUCTION
1-3