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Intel BX80532PG3200D Datasheet

Intel pentium processor on 45-nm process, platforms based on mobile intel 4 series express chipset family
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Intel® Pentium® Processor on
45-nm Process
Datasheet
For Platforms Based on Mobile Intel® 4 Series Express Chipset Family
October 2009
Document Number: 322875-001EN

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Summary of Contents for Intel BX80532PG3200D

  • Page 1 Intel® Pentium® Processor on 45-nm Process Datasheet For Platforms Based on Mobile Intel® 4 Series Express Chipset Family October 2009 Document Number: 322875-001EN...
  • Page 2 BIOS update. Software applications may not be compatible with all operating systems. Please check with your application vendor. Intel, Pentium, Centrino, Intel Core Duo, Intel SpeedStep, MMX and the Intel logo are trademarks of Intel Corporation in the U.S. and other countries.

  • Page 3: Table Of Contents

    2.1.1 Core Low-Power State Descriptions............13 2.1.2 Package Low-power State Descriptions............14 Enhanced Intel SpeedStep® Technology .............. 17 Extended Low-Power States................18 FSB Low Power Enhancements ................19 Processor Power Status Indicator (PSI-2) Signal ............ 19 Electrical Specifications ................... 21 Power and Ground Pins ..................
  • Page 4 Tables Coordination of Core Low-Power States at the Package Level..........13 Voltage Identification Definition ..................22 BSEL[2:0] Encoding for BCLK Frequency..............25 FSB Pin Groups ......................26 Processor Absolute Maximum Ratings................27 Voltage and Current Specifications for the Pentium Processors........29 AGTL+ Signal Group DC Specifications ................31 CMOS Signal Group DC Specifications................32 Open Drain Signal Group DC Specifications ..............32 Pin Name Listing ......................38...

  • Page 5: Revision History

    Revision History Document Revision Description Date Number Number 322875 -001 Initial Draft October 2009 § Datasheet...
  • Page 6 Datasheet...

  • Page 7: Introduction

    Introduction Introduction This document contains electrical, mechanical and thermal specifications for the following processors: • The Intel® Pentium® support the Mobile Intel® 4 Series Express Chipset and Intel® ICH9M I/O controller. Notes: In this document 1. Intel Pentium processor are referred to as the processor 2.

  • Page 8: Terminology

    This feature can prevent some classes of viruses or worms that exploit buffer overrun vulnerabilities and can thus help improve the overall security of the system. See the Intel® 64 and IA-32 Architectures Software Developer's Manuals for more detailed information.

  • Page 9: References

    Volume 2A: Instruction Set Reference, A-M 253666 Volume 2B: Instruction Set Reference, N-Z 253667 Volume 3A: System Programming Guide 253668 Volume 3B: System Programming Guide 253669 NOTE: Contact your Intel representative for the latest revision of this document. § Datasheet...
  • Page 10 Introduction Datasheet...

  • Page 11: Low Power Features

    Low Power Features Low Power Features Clock Control and Low-Power States The processor supports low-power states both at the individual core level and the package level for optimal power management. A core may independently enter the C1/AutoHALT, C1/MWAIT, C2, C3, low-power states.

  • Page 12: Core Low-Power States

    Low Power Features Figure 1. Core Low-Power States Stop Grant STPCLK# STPCLK# asserted de-asserted STPCLK# STPCLK# de-asserted asserted STPCLK# de-asserted C1/Auto STPCLK# asserted MWAIT Halt Core state HLT instruction break MWAIT(C1) Halt break P_LVL2 or MWAIT(C2) Core state break † Core P_LVL3 or state...

  • Page 13: Core Low-Power State Descriptions

    LINT[1:0] (NMI, INTR), or FSB interrupt messages. RESET# will cause the processor to immediately initialize itself. A System Management Interrupt (SMI) handler will return execution to either Normal state or the AutoHALT Powerdown state. See the Intel® 64 and IA-32 Architectures Software Developer's Manuals, Volume 3A/3B: System Programmer's Guide for more information.

  • Page 14: Package Low-Power State Descriptions

    MWAIT(C1) instruction. Processor behavior in the MWAIT state is identical to the AutoHALT state except that Monitor events can cause the processor core to return to the C0 state. See the Intel® 64 and IA-32 Architectures Software Developer's Manuals, Volume 2A: Instruction Set Reference, A-M and Volume 2B: Instruction Set Reference, N-Z, for more information.

  • Page 15: Sleep State

    Low Power Features RESET# causes the processor to immediately initialize itself, but the processor will stay in Stop-Grant state. When RESET# is asserted by the system, the STPCLK#, SLP#, DPSLP#, and DPRSTP# pins must be deasserted prior to RESET# deassertion as per AC Specification T45.
  • Page 16 Low Power Features 2.1.2.5 Deep Sleep State The Deep Sleep state is entered through assertion of the DPSLP# pin while in the Sleep state. BCLK may be stopped during the Deep Sleep state for additional platform-level power savings. BCLK stop/restart timings on appropriate GMCH-based platforms with the CK505 clock chip are as follows: •...

  • Page 17: Enhanced Intel Speedstep® Technology

    • Enhanced thermal management features: — Digital Thermal Sensor and Out of Specification detection. — Intel Thermal Monitor 1 (TM1) in addition to Intel Thermal Monitor 2 (TM2) in case of unsuccessful TM2 transition. — Dual-core thermal management synchronization.

  • Page 18: Extended Low-Power States

    Enhanced Intel SpeedStep Technology transition down to the lowest operating point. Upon receiving a break event from the package low-power state, control will be returned to software while an Enhanced Intel SpeedStep Technology transition up to the initial operating point occurs. The advantage of this feature is that it significantly reduces leakage while in the Stop-Grant state.

  • Page 19: Fsb Low Power Enhancements

    Low Power Features FSB Low Power Enhancements The processor incorporates FSB low power enhancements: • Dynamic FSB Power Down • BPRI# control for address and control input buffers • Dynamic Bus Parking • Dynamic On-Die Termination disabling • Low V (I/O termination voltage) •...
  • Page 20 Low Power Features Datasheet...

  • Page 21: Electrical Specifications

    Electrical Specifications Electrical Specifications Power and Ground Pins For clean, on-chip power distribution, the processor will have a large number of V (power) and V (ground) inputs. All power pins must be connected to V power planes while all V pins must be connected to system ground planes.

  • Page 22: Voltage Identification And Power Sequencing

    Electrical Specifications Voltage Identification and Power Sequencing The processor uses seven voltage identification pins,VID[6:0], to support automatic selection of power supply voltages. The VID pins for the processor are CMOS outputs driven by the processor VID circuitry. Table 2 specifies the voltage level corresponding to the state of VID[6:0].
  • Page 23 Electrical Specifications Table 2. Voltage Identification Definition (Sheet 2 of 3) VID6 VID5 VID4 VID3 VID2 VID1 VID0 1.0000 0.9875 0.9750 0.9625 0.9500 0.9375 0.9250 0.9125 0.9000 0.8875 0.8750 0.8625 0.8500 0.8375 0.8250 0.8125 0.8000 0.7875 0.7750 0.7625 0.7500 0.7375 0.7250 0.7125 0.7000...
  • Page 24 Electrical Specifications Table 2. Voltage Identification Definition (Sheet 3 of 3) VID6 VID5 VID4 VID3 VID2 VID1 VID0 0.4125 0.4000 0.3875 0.3750 0.3625 0.3500 0.3375 0.3250 0.3125 0.3000 0.2875 0.2750 0.2625 0.2500 0.2375 0.2250 0.2125 0.2000 0.1875 0.1750 0.1625 0.1500 0.1375 0.1250 0.1125...

  • Page 25: Catastrophic Thermal Protection

    Electrical Specifications Catastrophic Thermal Protection The processor supports the THERMTRIP# signal for catastrophic thermal protection. An external thermal sensor should also be used to protect the processor and the system against excessive temperatures. Even with the activation of THERMTRIP#, which halts all processor internal clocks and activity, leakage current can be high enough that the processor cannot be protected in all conditions without the removal of power to the processor.

  • Page 26: Fsb Signal Groups

    Electrical Specifications FSB Signal Groups The FSB signals have been combined into groups by buffer type in the following sections. In this document, the term “AGTL+ Input” refers to the AGTL+ input group as well as the AGTL+ I/O group when receiving. Similarly, “AGTL+ Output” refers to the AGTL+ output group as well as the AGTL+ I/O group when driving.

  • Page 27: Cmos Signals

    Electrical Specifications Refer to Chapter 4 for signal descriptions and termination requirements. In processor systems where there is no debug port implemented on the system board, these signals are used to support a debug port interposer. In systems with the debug port implemented on the system board, these signals are no connects.

  • Page 28: Processor Dc Specifications

    This rating applies to the processor and does not include any tray or packaging. Failure to adhere to this specification can affect the long-term reliability of the processor. For Intel® Pentium® processors in 22x22 mm package. 3.10 Processor DC Specifications The processor DC specifications in this section are defined at the processor core (pads) unless noted otherwise.

  • Page 29: Voltage And Current Specifications For The Pentium Processors

    Electrical Specifications Table 6. Voltage and Current Specifications for the Pentium Processors Symbol Parameter Unit Notes at Highest Frequency Mode (HFM) 1, 2 CCHFM at Lowest Frequency Mode (LFM) 0.85 — 1.15 1, 2 CCLFM Default V Voltage for Initial Power Up —...

  • Page 30: Active Vcc And Icc Loadline For Pentium Processors

    VID range. Note that this differs from the VID employed by the processor during a power management event (Intel Thermal Monitor 2, Enhanced Intel SpeedStep Technology, or Enhanced Halt State).

  • Page 31: Agtl+ Signal Group Dc Specifications

    Electrical Specifications Table 7. AGTL+ Signal Group DC Specifications Symbol Parameter Unit Notes I/O Voltage 1.00 1.05 1.10 GTLREF Reference Voltage 0.65 0.70 0.72 Compensation Resistor 27.23 27.5 27.78  COMP Termination Resistor Address  11, 12 ODT/A Termination Resistor Data ...

  • Page 32: Cmos Signal Group Dc Specifications

    Electrical Specifications Table 8. CMOS Signal Group DC Specifications Symbol Parameter Unit Notes I/O Voltage 1.00 1.05 1.10 Input Low Voltage CMOS -0.10 0.00 0.3*V Input High Voltage 0.7*V +0.1 Output Low Voltage -0.10 0.1*V Output High Voltage 0.9*V +0.1 Output Low Current —...

  • Page 33: Package Mechanical Specifications And Pin Information

    Package Mechanical Specifications and Pin Information Package Mechanical Specifications and Pin Information Package Mechanical Specifications The processor is available in 478-pin Micro-FCPGA packages. The package mechanical dimensions are shown in Figure 9 through Figure The mechanical package pressure specifications are in a direction normal to the surface of the processor.

  • Page 34: 1-Mb Die Micro-Fcpga Processor Package Drawing (Sheet 1 Of 2)

    Package Mechanical Specifications and Pin Information Figure 4. 1-MB die Micro-FCPGA Processor Package Drawing (Sheet 1 of 2) Datasheet...

  • Page 35: 1-Mb Die Micro-Fcpga Processor Package Drawing (Sheet 2 Of 2)

    Package Mechanical Specifications and Pin Information Figure 5. 1-MB Die Micro-FCPGA Processor Package Drawing (Sheet 2 of 2) Datasheet...

  • Page 36: Processor Pinout And Pin List

    Package Mechanical Specifications and Pin Information Processor Pinout and Pin List Figure 6 Figure 7 show the processor pinout as viewed from the top of the package. Table 10 provides the pin list, arranged numerically by pin number. For signal descriptions, refer to Section 4.3.

  • Page 37: Processor Pinout (Top Package View, Right Side)

    Package Mechanical Specifications and Pin Information Figure 7. Processor Pinout (Top Package View, Right Side) BCLK[1] BCLK[0] THRMDA TEST6 BSEL[0] BSEL[1] THRMDC VCCA DBR# BSEL[2] TEST1 TEST3 VCCA PROCHOT IERR# RSVD DPWR# TEST2 D[0]# D[7]# D[6]# D[2]# DRDY# D[4]# D[1]# D[13]# VCCP D[3]#...

  • Page 38: Pin Name Listing

    Package Mechanical Specifications and Pin Information Table 10. Pin Name Listing Signal Pin Name Pin # Buffer Direction Type Source Input/ A[3]# Synch Output Source Input/ A[4]# Synch Output Source Input/ A[5]# Synch Output Source Input/ A[6]# Synch Output Source Input/ A[7]# Synch...
  • Page 39 Package Mechanical Specifications and Pin Information Table 10. Pin Name Listing Signal Pin Name Pin # Buffer Direction Type Source Input/ A[24]# Synch Output Source Input/ A[25]# Synch Output Source Input/ A[26]# Synch Output Source Input/ A[27]# Synch Output Source Input/ A[28]# Synch...
  • Page 40 Package Mechanical Specifications and Pin Information Table 10. Pin Name Listing Signal Pin Name Pin # Buffer Direction Type Common BPRI# Input Clock Common Input/ BR0# Clock Output BSEL[0] CMOS Output BSEL[1] CMOS Output BSEL[2] CMOS Output Power/ Input/ COMP[0] Other Output Power/...
  • Page 41 Package Mechanical Specifications and Pin Information Table 10. Pin Name Listing Signal Pin Name Pin # Buffer Direction Type Source Input/ D[14]# Synch Output Source Input/ D[15]# Synch Output Source Input/ D[16]# Synch Output Source Input/ D[17]# Synch Output Source Input/ D[18]# Synch...
  • Page 42 Package Mechanical Specifications and Pin Information Table 10. Pin Name Listing Signal Pin Name Pin # Buffer Direction Type Source Input/ D[36]# Synch Output Source Input/ D[37]# Synch Output Source Input/ D[38]# Synch Output Source Input/ D[39]# Synch Output Source Input/ D[40]# Synch...
  • Page 43 Package Mechanical Specifications and Pin Information Table 10. Pin Name Listing Table 10. Pin Name Listing Signal Signal Pin Name Pin # Buffer Direction Pin Name Pin # Buffer Direction Type Type Source Input/ Source Input/ D[58]# AE21 DSTBP[2]# AA26 Synch Output Synch...
  • Page 44 Package Mechanical Specifications and Pin Information Table 10. Pin Name Listing Table 10. Pin Name Listing Signal Signal Pin Name Pin # Buffer Direction Pin Name Pin # Buffer Direction Type Type Common Power/ RS[1]# Input Clock Other Common Power/ RS[2]# Input Clock...
  • Page 45 Package Mechanical Specifications and Pin Information Table 10. Pin Name Listing Table 10. Pin Name Listing Signal Signal Pin Name Pin # Buffer Direction Pin Name Pin # Buffer Direction Type Type Power/ Power/ AB15 AE12 Other Other Power/ Power/ AB17 AE13 Other...
  • Page 46 Package Mechanical Specifications and Pin Information Table 10. Pin Name Listing Table 10. Pin Name Listing Signal Signal Pin Name Pin # Buffer Direction Pin Name Pin # Buffer Direction Type Type Power/ Power/ Other Other Power/ Power/ Other Other Power/ Power/ Other...
  • Page 47 Package Mechanical Specifications and Pin Information Table 10. Pin Name Listing Table 10. Pin Name Listing Signal Signal Pin Name Pin # Buffer Direction Pin Name Pin # Buffer Direction Type Type Power/ Power/ VCCP Other Other Power/ Power/ VCCP Other Other Power/...
  • Page 48 Package Mechanical Specifications and Pin Information Table 10. Pin Name Listing Table 10. Pin Name Listing Signal Signal Pin Name Pin # Buffer Direction Pin Name Pin # Buffer Direction Type Type Power/ Power/ AC14 AE26 Other Other Power/ Power/ AC16 Other Other...
  • Page 49 Package Mechanical Specifications and Pin Information Table 10. Pin Name Listing Table 10. Pin Name Listing Signal Signal Pin Name Pin # Buffer Direction Pin Name Pin # Buffer Direction Type Type Power/ Power/ Other Other Power/ Power/ Other Other Power/ Power/ Other...
  • Page 50 Package Mechanical Specifications and Pin Information Table 10. Pin Name Listing Table 10. Pin Name Listing Signal Signal Pin Name Pin # Buffer Direction Pin Name Pin # Buffer Direction Type Type Power/ Power/ Other Other Power/ Power/ Other Other Power/ Power/ Other...

  • Page 51: Pin # Listing

    Package Mechanical Specifications and Pin Information Table 10. Pin Name Listing Table 11. Pin # Listing Signal Signal Buffer Pin # Pin Name Direction Pin Name Pin # Buffer Direction Type Type Power/Other Power/ SMI# CMOS Input Other Power/Other Power/ Other FERR# Open Drain...
  • Page 52 Package Mechanical Specifications and Pin Information Table 11. Pin # Listing Table 11. Pin # Listing Signal Buffer Signal Buffer Pin # Pin Name Direction Pin # Pin Name Direction Type Type AA13 Power/Other Input/ AB22 D[51]# Source Synch Output AA14 Power/Other AB23...
  • Page 53 Package Mechanical Specifications and Pin Information Table 11. Pin # Listing Table 11. Pin # Listing Signal Buffer Signal Buffer Pin # Pin Name Direction Pin # Pin Name Direction Type Type BPM[1]# Common Clock Output AE13 Power/Other Input/ AE14 Power/Other BPM[0]# Common Clock...
  • Page 54 Package Mechanical Specifications and Pin Information Table 11. Pin # Listing Table 11. Pin # Listing Signal Buffer Signal Buffer Pin # Pin Name Direction Pin # Pin Name Direction Type Type Input/ Power/Other AF22 D[62]# Source Synch Output Power/Other Input/ Power/Other AF23...
  • Page 55 Package Mechanical Specifications and Pin Information Table 11. Pin # Listing Table 11. Pin # Listing Signal Buffer Signal Buffer Pin # Pin Name Direction Pin # Pin Name Direction Type Type PROCHOT Input/ Power/Other Open Drain Output RS[0]# Common Clock Input RSVD Reserved...
  • Page 56 Package Mechanical Specifications and Pin Information Table 11. Pin # Listing Table 11. Pin # Listing Signal Buffer Signal Buffer Pin # Pin Name Direction Pin # Pin Name Direction Type Type Input/ Input/ D[5]# Source Synch REQ[0]# Source Synch Output Output Power/Other...
  • Page 57 Package Mechanical Specifications and Pin Information Table 11. Pin # Listing Table 11. Pin # Listing Signal Buffer Signal Buffer Pin # Pin Name Direction Pin # Pin Name Direction Type Type Power/Other Input/ D[18]# Source Synch Output Input/ D[23]# Source Synch Output Input/...
  • Page 58 Package Mechanical Specifications and Pin Information Table 11. Pin # Listing Table 11. Pin # Listing Signal Buffer Signal Buffer Pin # Pin Name Direction Pin # Pin Name Direction Type Type Input/ Input/ A[18]# Source Synch D[43]# Source Synch Output Output Power/Other...

  • Page 59: Alphabetical Signals Reference

    Package Mechanical Specifications and Pin Information Alphabetical Signals Reference Table 12. Signal Description (Sheet 1 of 8) Name Type Description A[35:3]# (Address) define a 2 -byte physical memory address space. In sub-phase 1 of the address phase, these pins transmit the address of a transaction.
  • Page 60 Package Mechanical Specifications and Pin Information Table 12. Signal Description (Sheet 2 of 8) Name Type Description BPRI# (Bus Priority Request) is used to arbitrate for ownership of the FSB. It must connect the appropriate pins of both FSB agents. Observing BPRI# active (as asserted by the priority agent) causes BPRI# Input...
  • Page 61 Package Mechanical Specifications and Pin Information Table 12. Signal Description (Sheet 3 of 8) Name Type Description DEFER# is asserted by an agent to indicate that a transaction cannot be ensured in-order completion. Assertion of DEFER# is DEFER# Input normally the responsibility of the addressed memory or input/ output agent.
  • Page 62 For additional information on the pending break event functionality, including identification of support of the feature and enable/disable information, refer to Volumes 3A and 3B of the Intel® 64 and IA-32 Architectures Software Developer's Manuals and the Intel® Processor Identification and CPUID Instruction application note.
  • Page 63 Package Mechanical Specifications and Pin Information Table 12. Signal Description (Sheet 5 of 8) Name Type Description INIT# (Initialization), when asserted, resets integer registers inside the processor without affecting its internal caches or floating-point registers. The processor then begins execution at the power-on Reset vector configured during power-on configuration.
  • Page 64 Package Mechanical Specifications and Pin Information Table 12. Signal Description (Sheet 6 of 8) Name Type Description PWRGOOD (Power Good) is a processor input. The processor requires this signal to be a clean indication that the clocks and power supplies are stable and within their specifications. ‘Clean’ implies that the signal remains low (capable of sinking leakage current), without glitches, from the time that the power supplies PWRGOOD...
  • Page 65 Package Mechanical Specifications and Pin Information Table 12. Signal Description (Sheet 7 of 8) Name Type Description STPCLK# (Stop Clock), when asserted, causes the processor to enter a low power Stop-Grant state. The processor issues a Stop- Grant Acknowledge transaction, and stops providing internal clock signals to all processor core units except the FSB and APIC units.
  • Page 66 Package Mechanical Specifications and Pin Information Table 12. Signal Description (Sheet 8 of 8) Name Type Description VCCSENSE together with VSSSENSE are voltage feedback signals VCCSENSE Output that control the 2.1 m loadline at the processor die. It should be used to sense voltage near the silicon with little noise.

  • Page 67: Thermal Specifications And Design Considerations

    A complete thermal solution includes both component and system-level thermal management features. To allow for the optimal operation and long-term reliability of Intel processor-based systems, the system/processor thermal solution should be designed so the processor remains within the minimum and maximum junction...

  • Page 68: Power Specifications For The Pentium Processors

    As measured by the activation of the on-die Intel Thermal Monitor. The Intel Thermal Monitor’s automatic mode is used to indicate that the maximum T has been reached.

  • Page 69: Monitoring Die Temperature

    • Digital Thermal Sensor 5.1.1 Thermal Diode Intel’s processors utilize an SMBus thermal sensor to read back the voltage/current characteristics of a substrate PNP transistor. Since these characteristics are a function of temperature, these parameters can be used to calculate silicon temperature values.

  • Page 70: Intel® Thermal Monitor

    Series Resistance  NOTES: Intel does not support or recommend operation of the thermal diode under reverse bias. Characterized across a temperature range of 50-105°C. Not 100% tested. Specified by design characterization. The ideality factor, nQ, represents the deviation from ideal transistor model behavior as...
  • Page 71 Enhanced Intel SpeedStep Technology target frequency point. The TCC may also be activated via on-demand mode. If bit 4 of the ACPI Intel Thermal Monitor control register is written to a 1, the TCC will be activated immediately independent of the processor temperature.

  • Page 72: Digital Thermal Sensor

    ACPI register, one performance counter register, three MSR, and one I/O pin (PROCHOT#). All are available to monitor and control the state of the Intel Thermal Monitor feature. The Intel Thermal Monitor can be configured to generate an interrupt upon the assertion or deassertion of PROCHOT#.

  • Page 73: Out Of Specification Detection

    Changes to the temperature can be detected via two programmable thresholds located in the processor MSRs. These thresholds have the capability of generating interrupts via the core's local APIC. Refer to the Intel® 64 and IA-32 Architectures Software Developer's Manuals for specific register and programming details.
  • Page 74 Thermal Specifications and Design Considerations of time when running the most power-intensive applications. An under-designed thermal solution that is not able to prevent excessive assertion of PROCHOT# in the anticipated ambient environment may cause a noticeable performance loss. § Datasheet...

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Pentium series

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