R-Box Box Level Pmon State; R-Box Pmon State - Counter/Control Pairs + Filters; Table 2-41. R_Msr_Pmon_Global_Ctl_{15_8, 7_0} Register Fields; Table 2-42. R_Msr_Pmon_Global_Status_{15_8, 7_0} Register Fields - Intel BX80571E7500 - Core 2 Duo 2.93 GHz Processor Programming Manual

I ® X ® P 7500 S
NTEL EON ROCESSOR
2.6.3.2

R-Box Box Level PMON state

The following registers represent the state governing all box-level PMUs in the R-Box.
The _GLOBAL_CTL register contains the bits used to enable monitoring. It is necessary to set the
.ctr_en bit to 1 before the corresponding data register can collect events.
If an overflow is detected from one of the R-Box PMON registers, the corresponding bit in the
_GLOBAL_STATUS.ov field will be set. To reset the overflow bits set in the _GLOBAL_STATUS.ov field, a
user must set the corresponding bits in the _GLOBAL_OVF_CTL.clr_ov field before beginning a new
sample interval.

Table 2-41. R_MSR_PMON_GLOBAL_CTL_{15_8, 7_0} Register Fields

Field
ctr_en

Table 2-42. R_MSR_PMON_GLOBAL_STATUS_{15_8, 7_0} Register Fields

Field
ov

Table 2-43. R_MSR_PMON_OVF_CTL_{15_8, 7_0} Register Fields

Field
clr_ov
2.6.3.3

R-Box PMON state - Counter/Control Pairs + Filters

The following table defines the layout of the R-Box performance monitor control registers. The main
task of these configuration registers is to select the subcontrol register that selects the event to be
monitored by the respective data counter. Setting the .ev_sel fields performs the subcontrol register
selection. The .en bit must be set to 1 to enable counting.
Additional control bits include:
- .pmi_en governs what to do if an overflow is detected.
U P G
ERIES NCORE ROGRAMMING UIDE
HW
Bits Reset
Val
7:0 0 Must be set to enable each RBOX counter (bit 0 to enable ctr0, etc)
NOTE: U-Box enable and per counter enable must also be set to fully
enable the counter.
HW
Bits Reset
Val
7:0 0 If an overflow is detected from the corresponding RBOX PMON register,
it's overflow bit will be set.
HW
Bits Reset
Val
7:0 0 Writing bit in field to '1' will clear the corresponding overflow bit in
R_CSR_PMON_GLOBAL_STATUS_{15_8,7_0} to 0.
UNCORE PERFORMANCE MONITORING
Description
Description
Description
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