R-Box Iperf Performance Monitoring Control Registers; Table 2-48. R_Msr_Port{7-0}_Iperf_Cfg{1-0} Registers - Intel BX80571E7500 - Core 2 Duo 2.93 GHz Processor Programming Manual

I ® X ® P 7500 S
NTEL EON ROCESSOR
2.6.3.4

R-Box IPERF Performance Monitoring Control Registers

The following table contains the events that can be monitored if one of the RIX (IPERF) registers was
chosen to select the event.
Field
FLT_SENT
NULL_IDLE
RETRYQ_OV
RETRYQ_NE
OUTQ_OV
OUTQ_NE
RCVD_SPEC_FLT
RCVD_ERR_FLT
ig
MC_ROLL_ALLOC
MC
EOT_NE
ARB_SEL
U P G
ERIES NCORE ROGRAMMING UIDE
Table 2-48. R_MSR_PORT{7-0}_IPERF_CFG{1-0} Registers (Sheet
HW
Bits Reset
Val
31 0x0 Flit Sent
30 0x0 Null Idle Flit Sent
29 0x0 Retry Queue Overflowed in this Output Port.
28 0x0 Retry Queue Not Empty in this Output Port
27 0x0 Output Queue Overflowed in this Ouput Port
26 0x0 Output Queue Not Empty in this Output Port
25 0x0 Special Flit Received
24 0x0 Flit Received which caused CRC Error
23:22 0x0 Read zero; writes ignored. (?)
21 0x0 Used with MC field. If set, every individual allocation of selected MC
into EOT is reported. If 0, a 'rolling' count is reported (count
whenever count overflows 7b count - val of 128) for selected MC's
allocation into EOT.
20:17 0x0 EOT Message Class Count
1000: Data Response - VN1
0111: Non-Coherent Standard
0110: Non-Coherent Bypass
0101: Snoop
0100: Data Response - VN0
0011: Non-Data Response
0010: Home VN1
0001: Home VN0
16 0x0 Count cycles that EOT is not Empty
15:9 0x00 Allocation to Arb Select Bit Mask:
0b1XXXXXX: Home VN0
0bX1XXXXX: Home VN1
0bXX1XXXX: Snoop
0bXXX1XXX: Non-Data Response
0bXXXX1XX: Data Response - VN0/VN1
0bXXXXX1X: Non-Coherent Standard
0bXXXXXX1: Non-Coherent Bypass
UNCORE PERFORMANCE MONITORING
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Description
2-82