Intel BX80571E7500 - Core 2 Duo 2.93 GHz Processor Programming Manual page 126

I ® X ® P 7500 S
NTEL EON ROCESSOR
Extension
CAS_WR_CLS.WRPRIO
CAS_WR_CLS.ADAPTIVE
MRS
RFR
ENSR
EXSR
NOP
TRKL
PRE
SYNC
CKE_HI
CKE_LO
SOFT_RST
WR_CFG
RD_CFG
ZQCAL
ALL.TRDOFF
ALL.RDPRIO
ALL.WRPRIO
ALL.ADAPT
DSP_FILL
• Title: Dispatch Queue Events
• Category: DSP Events
• Event Code: 0x00, Max. Inc/Cyc: 1,
• Definition: Measure a dispatch queue event.
Extension
RDQ_FULL
WRQ_FULL
RDQ_EMPTY
WRQ_EMPTY
FVC_EV0
• Title: FVC Event 0
• Category: FVC Events
• Event Code: 0x0d, Max. Inc/Cyc: 1,
• Definition: Measure an FVC related event.
• NOTE: It is possible to program the FVC register such that up to 4 events from the FVC can be inde-
pendently monitored. However, the bcmd_match and resp_match subevents depend on the setting of
additional bits in the FVC register (11:9 and 8:5 respectively). Therefore, only ONE
U P G
ERIES NCORE ROGRAMMING UIDE
PLD Dep
Bits
[12:8]0x6
&& [0]0x1
[12:8]0x6
&& [0]0x1
[12:8]0x7
[12:8]0x9
[12:8]0xA
[12:8]0xB
[12:8]0xC
[12:8]0x10
[12:8]0x11
[12:8]0x12
[12:8]0x14
[12:8]0x15
[12:8]0x17
[12:8]0x1C
[12:8]0x1D
[12:8]0x1E
[0]0x0
[0]0x0
[0]0x0
[0]0x0
Table 2-88. Unit Masks for DSP_FILL
DSP[10:7]
0x1
0x2
0x4
0x8
UNCORE PERFORMANCE MONITORING
ISS Dep
Bits
[9:7]0x2 Count CAS Write (precharge, closed page mode) DRAM
commands during 'static write priority' scheduling
mode.
[9:7]0x3 Count CAS Write (precharge, closed page mode) DRAM
commands during 'adaptive' scheduling mode.
Count Mode register set DRAM commands
Count Refresh DRAM commands.
Count Enter Self-Refresh DRAM commands.
Count Exit Self-Refresh DRAM commands.
Count NOP DRAM commands.
Count Write Trickle DRAM commands.
Count PRE DRAM commands.
Count SYNC DRAM commands.
Count CKE High DRAM commands.
Count CKE Low DRAM commands.
Count Soft Reset DRAM commands.
Count Write Configuration Register DRAM commands.
Count Read Configuration Register DRAM commands.
Count ZQ Calibration DRAM commands.
[9:7]0x0 Count all DRAM commands during "static trade off"
scheduling mode
[9:7]0x1 Count all DRAM commands during "static read priority"
scheduling mode
[9:7]0x2 Count all DRAM commands during "static write
priority" scheduling mode
[9:7]0x3 Count all DRAM commands during "adaptive"
scheduling mode
Description
Cycles dispatch read queue is full
Cycles dispatch write queue is full
Cycles dispatch read queue is empty
Cycles dispatch write queue is empty
Description
2-114