Intel BV80605001914AG - Processor - 1 x Xeon X3430 Specification
Specification update
Hide thumbs
Also See for BV80605001914AG - Processor - 1 x Xeon X3430:
Table of Contents
Related Manuals for Intel BV80605001914AG - Processor - 1 x Xeon X3430
Summary of Contents for Intel BV80605001914AG - Processor - 1 x Xeon X3430
- Page 1 ® ® Intel Xeon Processor 3400 Series Specification Update May 2010 322373-009 Reference Number:...
- Page 2 It may also require modifications of implementation of new business processes. With regard to notebooks, Intel AMT may not be available or certain capabilities may be limited over a host OS-based VPN or when connecting wirelessly, on battery power, sleeping, hibernating or powered off.
-
Page 3: Table Of Contents
Contents Contents Revision History ....................... 5 Preface ..........................6 Summary Tables of Changes ..................8 Identification Information ....................16 Errata ..........................19 Specification Changes....................55 Specification Clarifications ................... 56 Documentation Changes ....................57 § Specification Update... - Page 4 Contents Specification Update...
-
Page 5: Revision History
January 2010 -006 Added Errata AAO115 and AAO116. February 2010 -007 Added Erratum AAO17. March 2010 -008 Added Errata AAO18 and AAO19. April 2010 -009 Updated the Processor Identification Table to include Intel® Xeon® Processor X3480 May 2010 Specification Update... -
Page 6: Preface
Volume 3A: System Programming Guide ® Intel 64 and IA-32 Architectures Software Developer’s Manual, Volume 3B: System Programming Guide ® Intel 64 and IA-32 Intel Architecture Optimization Reference Manual http://www.intel.com/ ® Intel 64 and IA-32 Architectures Software Developer’s Manual design/processor/ Documentation Changes specupdt/252046.htm... - Page 7 Nomenclature Errata are design defects or errors. These may cause the processor behavior to deviate from published specifications. Hardware and software designed to be used with any given stepping must assume that all errata documented for that stepping are present on all devices. S-Spec Number is a five-digit code used to identify products.
-
Page 8: Summary Tables Of Changes
Summary Tables of Changes The following tables indicate the errata, specification changes, specification clarifications, or documentation changes which apply to the processor. Intel may fix some of the errata in a future stepping of the component, and account for the other outstanding issues through documentation or specification changes as noted. - Page 9 Each Specification Update item is prefixed with a capital letter to distinguish the product. The key below details the letters that are used in Intel’s microprocessor Specification Updates: ® ® Intel Xeon processor 7000 sequence ® ® Intel Celeron processor ®...
- Page 10 Core™ i7-900 mobile processor Extreme Edition Series, Intel Core™ i7-800 and i7- 700 mobile processor series ® AAT = Intel Core™ i7-600, i5-500, i5-400 and i3-300 mobile processor series AAU = Intel® Core™ i5-600, i3-500 desktop processor series and Intel® Pentium® Processor G6950 Specification Update...
- Page 11 Errata (Sheet 1 of 5) Steppings Number Status ERRATA AAO1 No Fix The Processor May Report a #TS Instead of a #GP Fault REP MOVS/STOS Executing with Fast Strings Enabled and Crossing Page AAO2 No Fix Boundaries with Inconsistent Memory Types may use an Incorrect Data Size or Lead to Memory-Ordering Violations Code Segment Limit/Canonical Faults on RSM May be Serviced before Higher AAO3...
- Page 12 Errata (Sheet 2 of 5) Steppings Number Status ERRATA Synchronous Reset of IA32_APERF/IA32_MPERF Counters on Overflow Does Not AAO27 No Fix Work Disabling Thermal Monitor While Processor is Hot, Then Re-enabling, May Result in AAO28 No Fix Stuck Core Operating Ratio AAO29 No Fix PECI Does Not Support PCI Configuration Reads/Writes to Misaligned Addresses...
- Page 13 Errata (Sheet 3 of 5) Steppings Number Status ERRATA AAO55 No Fix Performance Monitor Counters May Count Incorrectly Processor Forward Progress Mechanism Interacting With Certain MSR/CSR Writes No Fix AAO56 May Cause Unpredictable System Behavior Performance Monitor Event Offcore_response_0 (B7H) Does Not Count NT Stores AAO57 No Fix to Local DRAM Correctly...
- Page 14 VM Exits Due to EPT Violations Do Not Record Information About Pre-IRET NMI AAO84 No Fix Blocking Intel® VT-d Receiving Two Identical Interrupt Requests May Corrupt Attributes of AAO85 No Fix Remapped Interrupt or Hang a Subsequent Interrupt-Remap-Cache Invalidation Command...
-
Page 15: Errata
FP Data Operand Pointer May Be Incorrectly Calculated After an FP Access Which AAO117 No Fix Wraps a 4-Gbyte Boundary in Code That Uses 32-Bit Address Size in 64-bit Mode IOTLB Invalidations Not Completing on Intel ® VT-d Engine for Integrated High AAO118 No Fix Definition Audio... -
Page 16: Identification Information
Identification Information Component Identification via Programming Interface The Intel Xeon processor 3400 series stepping can be identified by the following register contents: Extended Extended Processor Family Model Stepping Reserved Reserved Family Model Type Code Number 31:28 27:20 19:16 15:14 13:12... - Page 17 Processor Production Top-side Markings (Example) INTEL ©'08 PROC# BRAND SLxxx [COO] SPEED/CACHE [FPO] LOT NO S/N Table 1. Processor Identification (Sheet 1 of 2) Max Intel® Core Frequency Shared Turbo Boost S-Spec Processor Processor Stepping (GHz) / Technology L3 Cache...
- Page 18 VT-x) enabled. ® ® Intel Virtualization Technology for Directed I/O (Intel VT-d) enabled. This processor has TDP of 45 W. The core frequency reported in the processor brand string is rounded to 2 decimal digits. (For example, core frequency of 3.4666, repeating 6, is reported as @3.47 in brand string. Core frequency of 3.3333, is reported as @3.33 in brand string.)
-
Page 19: Errata
Under certain conditions as described in the Software Developers Manual section "Out- of-Order Stores For String Operations in Pentium 4, Intel Xeon, and P6 Family Processors" the processor performs REP MOVS or REP STOS as fast strings. Due to this... - Page 20 #GP fault may not match the non-canonical address that caused the fault. Implication: Operating systems may observe a #GP fault being serviced before higher priority Interrupts and Exceptions. Intel has not observed this erratum on any commercially available software. Workaround: None identified.
- Page 21 AAO5. Premature Execution of a Load Operation Prior to Exception Handler Invocation Problem: If any of the below circumstances occur, it is possible that the load portion of the instruction will have executed before the exception handler is entered. • If an instruction that performs a memory load causes a code segment limit violation.
- Page 22 AAO7. Incorrect Address Computed For Last Byte of FXSAVE/FXRSTOR Image Leads to Partial Memory Update Problem: A partial memory state save of the 512-byte FXSAVE image or a partial memory state restore of the FXRSTOR image may occur if a memory address exceeds the 64KB limit while the processor is operating in 16-bit mode or if a memory address exceeds the 4GB limit while the processor is operating in 32-bit mode.
- Page 23 ENTER instructions. This erratum is not expected to occur in ring 3. Faults are usually processed in ring 0 and stack switch occurs when transferring to ring 0. Intel has not observed this erratum on any commercially available software.
- Page 24 The MONITOR instruction only functions correctly if the specified linear address range is of the type write-back. CLFLUSH flushes data from the cache. Intel has not observed this erratum with any commercially available software. Workaround: Do not execute MONITOR or CLFLUSH instructions on the local xAPIC address space.
- Page 25 Developer’s Manual Volume 3A: System Programming Guide, Part 1, in the section titled "Switching to Protected Mode" recommends the FAR JMP immediately follows the write to CR0 to enable protected mode. Intel has not observed this erratum with any commercially available software.
- Page 26 If the segment selector descriptor straddles the canonical boundary, the error code pushed onto the stack may be incorrect. Implication: An incorrect error code may be pushed onto the stack. Intel has not observed this erratum with any commercially available software. Workaround: None identified.
- Page 27 Stack Segment and Stack Pointer. If MOV SS/POP SS is not followed by a MOV [r/e]SP, [r/e]BP, there may be a mismatched Stack Segment and Stack Pointer on any exception. Intel has not observed this erratum with any commercially available software or system.
- Page 28 Thermal Monitor disable. This condition will only correct itself once the processor reaches its TCC activation temperature again. Implication: Since Intel requires that Thermal Monitor be enabled in order to be operating within specification, this erratum should never be seen during normal operation. Workaround: Software should not disable Thermal Monitor during processor operation.
- Page 29 AAO30. OVER Bit for IA32_MCi_STATUS Register May Get Set on Specific lnternal Error Problem: If a specific type of internal unclassified error is detected, as identified by IA32_MCi_STATUS.MCACOD=0x0405, the IA32_MCi_ STATUS.OVER (overflow) bit [62] may be erroneously set. Implication: The OVER bit of the MCi_STATUS register may be incorrectly set for a specific internal unclassified error.
- Page 30 AAO33. xAPIC Timer May Decrement Too Quickly Following an Automatic Reload While in Periodic Mode Problem: When the xAPIC Timer is automatically reloaded by counting down to zero in periodic mode, the xAPIC Timer may slip in its synchronization with the external clock. The xAPIC timer may be shortened by up to one xAPIC timer tick.
- Page 31 Implication: Memory ordering may be violated. Intel has not observed this erratum with any commercially available software. Workaround: Software should ensure pages are not being actively used before requesting their memory type be changed.
- Page 32 However, the pending interrupt event will not be cleared. Implication: Due to this erratum, an infinite stream of interrupts will occur on the core servicing the external interrupt. Intel has not observed this erratum with any commercially available software/system. Workaround: None identified.
- Page 33 AAO43. FREEZE_WHILE_SMM Does Not Prevent Event From Pending PEBS During SMM Problem: In general, a PEBS record should be generated on the first count of the event after the counter has overflowed. However, IA32_DEBUGCTL_MSR.FREEZE_WHILE_SMM (MSR 1D9H, bit [14]) prevents performance counters from counting during SMM (System Management Mode).
- Page 34 AAO46. An Uncorrectable Error Logged in IA32_CR_MC2_STATUS May also Result in a System Hang Problem: Uncorrectable errors logged in IA32_CR_MC2_STATUS MSR (409H) may also result in a system hang causing an Internal Timer Error (MCACOD = 0x0400h) to be logged in another machine check bank (IA32_MCi_STATUS).
- Page 35 10B (All Including Self) or 11B (All Excluding Self). Implication: When this erratum occurs, cores which are in a sleep state may not wake up to handle the broadcast IPI. Intel has not observed this erratum with any commercially available software. Workaround: Use destination shorthand of 10B or 11B to send broadcast IPIs.
- Page 36 The aliasing of memory regions, a condition necessary for this erratum to occur, ® is documented as being unsupported in the Intel 64 and IA-32 Intel Architecture Software Developer's Manual, Volume 3A, in the section titled Programming the PAT.
- Page 37 None identified. Although the EFLAGS value saved by an affected event (a page fault or an EPT-induced VM exit) may contain incorrect arithmetic flag values, Intel has not identified software that is affected by this erratum. This erratum will have no further effects once the original instruction is restarted because the instruction will produce the same results as if it had initially completed without fault or VM exit.
- Page 38 AAO59. System May Hang if MC_CHANNEL_{0,1}_MC_DIMM_INIT_CMD.DO_ZQCL Commands Are Not Issued in Increasing Populated DDR3 Rank Order Problem: ZQCL commands are used during initialization to calibrate DDR3 termination. A ZQCL command can be issued by writing 1 to the MC_CHANNEL_{0,1}_MC_DIMM_INIT_CMD.DO_ZQCL (Device 4,5,6, Function 0, Offset 15, bit[15]) field and it targets the DDR3 rank specified in the RANK field (bits[7:5]) of the same register.
- Page 39 AAO62. Memory Intensive Workloads with Core C6 Transitions May Cause System Hang Problem: Under a complex set of internal conditions, a system running a high cache stress and I/ O workload combined with the presence of frequent core C6 transitions may result in a system hang.
- Page 40 Rapid Core C3/C6 Transitions May Cause Unpredictable System Behavior Problem: Under a complex set of internal conditions, cores rapidly performing C3/C6 transitions ® in a system with Intel Hyper-Threading Technology enabled may cause a machine check error (IA32_MCi_STATUS.MCACOD = 0x0106), system hang or unpredictable system behavior. Implication: This erratum may cause a machine check error, system hang or unpredictable system behavior.
- Page 41 AAO70. CPURESET Bit Does Not Get Cleared Problem: CPURESET (bit 10 of SYRE Device 8; Function 2; Offset 0CCH) allows the processor to be independently reset without assertion of the PLTRST# signal upon a 0 to 1 transition. The CPURESET bit does not get cleared and must be cleared by software. Implication: The processor will not be reset if a 1 is written to this bit while it is already a one.
- Page 42 Implication: Due to this erratum, updates to segment descriptors may not be preserved. Intel has not observed this erratum with any commercially available software or system. Workaround: It is possible for the BIOS to contain a workaround for this erratum.
- Page 43 Problem: x87 instructions that trigger #MF normally service interrupts before the #MF. Due to this erratum, if an instruction that triggers #MF is executed while Enhanced Intel SpeedStep® Technology transitions, Intel® Turbo Boost Technology transitions, or Thermal Monitor events occur, the pending #MF may be signaled before pending interrupts are serviced.
- Page 44 Unpredictable PCI Behavior Accessing Non-existent Memory Space Problem: Locked instructions whose memory reference is split across cache line boundaries and are aborted on PCI behind Intel® 5 Series Chipset and Intel® 3400 Series Chipset may cause subsequent PCI writes to be unpredictable. Implication:...
- Page 45 Status: For the steppings affected, see the Summary Tables of Changes. AAO86. S1 Entry May Cause Cores to Exit C3 or C6 C-State Problem: Under specific circumstances, S1 entry may cause a logical processor to spuriously wake up from C3 or C6 and transition to a C0/S1 state. Upon S1 exit, these logical processors will be operating in C0.
- Page 46 0, and the use of appropriate temperature smoothing filters in the range -100 to 0 to minimize fan speed fluctuations, if any, due to these errors. Intel does not recommend initiating system shutdown solely based on PECI readings. For systems...
- Page 47 AAO93. PECI PCIConfigRd() Followed by a GetTemp() May Cause System Hang in Package C6 State Problem: The PECI (Platform Environment Control Interface) PCIConfigRd() command immediately followed by a PECI GetTemp() command may result in a system hang. Implication: When the processor is in the package C6 state, a PECI PCIConfigRd() command immediately followed by a GetTemp() command may result in a system hang.
- Page 48 This erratum only occurs when IA32_FIXED_CTR0 overflows and the processor and counter are configured as follows: • Intel® Hyper-Threading Technology is enabled • IA32_FIXED_CTR0 local and global controls are enabled • IA32_FIXED_CTR0 is set to count events only on its own thread (IA32_FIXED_CTR_CTRL MSR (38DH) bit [2] = ‘0)
- Page 49 If Intel® Hyper-Threading Technology is disabled, the Performance Monitor events STORE_BLOCKS.NOT_STA and STORE_BLOCKS.STA may indicate a higher occurrence of loads blocked by stores than have actually occurred. If Intel Hyper-Threading Technology is enabled, the counts of loads blocked by stores may be unpredictable and they could be higher or lower than the correct count.
- Page 50 The count value for Performance Monitoring Event FP_MMX_TRANS_TO_MMX may be lower than expected. The degree of undercounting is dependent on the occurrences of the erratum condition while the counter is active. Intel has not observed this erratum with any commercially available software.
- Page 51 In a complex set of internal conditions when the processor exits from Core C6 state, it is possible that an interrupt may be dropped. Implication: Due to this erratum, an interrupt may be dropped. Intel has not observed this erratum with any commercially available software. Workaround: It is possible for the BIOS to contain a workaround for this erratum.
- Page 52 Implication: Due to this erratum, a livelock may occur that can only be terminated by a processor reset. Intel has not observed this erratum with any commercially available software. Workaround: None identified. Status: For the steppings affected, see the Summary Tables of Changes.
- Page 53 When Intel VT-d engine for integrated High Definition Audio device is enabled and software requests for IOTLB invalidation while audio traffic is active, the request may not complete and may result in a software hang. Intel has not observed this erratum with any commercially available software.
- Page 54 Workaround: None identified. Status: For the steppings affected, see the Summary Tables of Changes. Specification Update...
-
Page 55: Specification Changes
Specification Changes The Specification Changes listed in this section apply to the following documents: ® ® • Intel Xeon Processor 3400 Series Datasheet – Volumes 1 and 2 ® • Intel 64 and IA-32 Architectures Software Developer’s Manual, Volume 1: Basic Architecture ®... -
Page 56: Specification Clarifications
Specification Clarifications The Specification Clarifications listed in this section may apply to the following documents: ® ® • Intel Xeon Processor 3400 Series Datasheet – Volumes 1 and 2 ® • Intel 64 and IA-32 Architectures Software Developer’s Manual, Volume 1: Basic Architecture ®... -
Page 57: Documentation Changes
All Documentation Changes will be incorporated into a future version of the appropriate Processor documentation. ® Note: Documentation changes for Intel 64 and IA-32 Architecture Software Developer's Manual volumes 1, 2A, 2B, 3A, and 3B will be posted in a separate ®... - Page 58 RevisionNumberNDA: ...................-001 Ref_Num_NDA_LFD: ............. CDI / IBL #: 422224 Ref_Num_NDA_LFD_SVR:............CDI / IBL #: 422225 DatePUB: ..................October 2009 RevisionNumberPUB: ...................-001 ReferenceNumberPUB: .................. TBD Other Variables: Title: ................Intel® Core™ i7 Processor DocumentStatus: ..............Intel Confidential Specification Update, March 2008...
- Page 59 Specification Update, October 2009...
- Page 60 Specification Update, March 2008...
- Page 61 Specification Update, October 2009...
- Page 62 Specification Update, March 2008...
- Page 63 Revision History ....................... 5 Preface ..........................6 Summary Tables of Changes ..................8 Identification Information ....................16 Errata ..........................19 Specification Changes....................55 Specification Clarifications ................... 56 Documentation Changes ....................57 Specification Update,...