Intel BX80571E7500 - Core 2 Duo 2.93 GHz Processor Programming Manual page 130

Xeon processor series uncore programming guide
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I
® X
® P
7500 S
NTEL
EON
ROCESSOR
Extension
BBOX_RSP.COR
BBOX_RSP.UNCOR
BBOX_RSP.SPEC_ACK
BBOX_RSP.SPR_ACK
---
BBOX_RSP.SPR_UNCOR
SMI_NB_TRIG
FVID_RACE
• Title: FVID Race Detected
• Category: Misc
• Event Code: 0x18, Max. Inc/Cyc: 1,
• Definition: Number of FVID (Fill Victim Index) races detected.
• NOTE: This is a race condition where an IMT entry is recycled prematurely. It should not be observ-
able in hardware.
INFLIGHT_CMDS
• Title: In-flight Commands
• Category: M-Box Commands Received
• Event Code: 0x1d, Max. Inc/Cyc: 1,
• Definition: Number of new memory controller (read and write) commands accepted
FRM_TYPE
• Title: Frame (Intel SMI) Types
• Category: DRAM Commands
• Event Code: 0x09, Max. Inc/Cyc: 1,
• Definition: Count ISS Related Intel SMI Frame Type Events
Extension
FRM_TYPE_3CMD
FRM_TYPE_WDAT
FRM_TYPE_SYNC
FRM_TYPE_CHNL
---
FRM_TYPE_NOP
---
FRM_TYPE_1CMD
---
U
P
G
ERIES
NCORE
ROGRAMMING
UIDE
Table 2-92. Unit Masks for FVC_EV3 (Sheet 2 of 2)
FVC
FVC
[22:20]
[10:8]
0x6
0x2
0x6
0x3
0x6
0x4
0x6
0x5
0x6
0x6
0x6
0x7
0x7
ISS[3:0]
Bits
0x0
Counts 3CMD (3-command) Intel SMI frames
0x1
Counts WDAT (Write Data) Intel SMI frames
0x2
Counts SYNC Intel SMI frames
0x3
Counts CHNL (channel) Intel SMI frames
0x7-0x4
(*illegal selection*)
0x8
Counts nop Intel SMI frames
0xb-0x9
(*illegal selection*)
0xc
Counts all 1CMD (1-command) Intel SMI frames
0xf-0xd
(*illegal selection*)
UNCORE PERFORMANCE MONITORING
FVC
Description
[7:5]
Counts corrected (for example, after error trials or
just by a retry)
Count Uncorrectable Responses.
Speculative positive acknowledgement for optimized
read flow. No error was detected for the transaction.
Count positive acknowledgements for command to
misbehaving DIMM during sparing. No error was
detected for the transaction.
(*nothing will be counted*)
Counts Uncorrectable responses to B-Box as a result
of commands issued to misbehaving DIMM during
sparing
Select Intel SMI Northbound debug event bits from
Intel SMI status frames as returned from the Intel
7500 Scalable Memory Buffers. Used for Debug
purposes
Description
2-118

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