B-Box Performance Monitors; B-Box Box Level Pmon State; B-Box Performance Monitoring Msrs - Intel BX80571E7500 - Core 2 Duo 2.93 GHz Processor Programming Manual

I ® X ® P 7500 S
NTEL EON ROCESSOR
2.4.3

B-BOX Performance Monitors

BB1_CR_B_MSR_MASK
BB1_CR_B_MSR_MATCH
BB0_CR_B_MSR_MASK
BB0_CR_B_MSR_MATCH
BB1_CR_B_MSR_PERF_CNT3_REG
BB1_CR_B_MSR_PERF_CTL3_REG
BB1_CR_B_MSR_PERF_CNT2_REG
BB1_CR_B_MSR_PERF_CTL2_REG
BB1_CR_B_MSR_PERF_CNT1_REG
BB1_CR_B_MSR_PERF_CTL1_REG
BB1_CR_B_MSR_PERF_CNT0_REG
BB1_CR_B_MSR_PERF_CTL0_REG
BB1_CR_C_MSR_PMON_GLOBAL_OVF_CTL
BB1_CR_B_MSR_PMON_GLOBAL_STATUS
BB1_CR_B_MSR_PERF_GLOBAL_CTL
BB0_CR_B_MSR_PERF_CNT3_REG
BB0_CR_B_MSR_PERF_CTL3_REG
BB0_CR_B_MSR_PERF_CNT2_REG
BB0_CR_B_MSR_PERF_CTL2_REG
BB0_CR_B_MSR_PERF_CNT1_REG
BB0_CR_B_MSR_PERF_CTL1_REG
BB0_CR_B_MSR_PERF_CNT0_REG
BB0_CR_B_MSR_PERF_CTL0_REG
BB0_CR_C_MSR_PMON_GLOBAL_OVF_CTL
BB0_CR_B_MSR_PMON_GLOBAL_STATUS
BB0_CR_B_MSR_PERF_GLOBAL_CTL
2.4.3.1

B-Box Box Level PMON state

The following registers represent the state governing all box-level PMUs in the B-Box.
The _GLOBAL_CTL register contains the bits used to enable monitoring. It is necessary to set the
.ctr_en bit to 1 before the corresponding data register can collect events.
If an overflow is detected from one of the B-Box PMON registers, the corresponding bit in the
_GLOBAL_STATUS.ov field will be set. To reset the overflow bits set in the _GLOBAL_STATUS.ov field, a
user must set the corresponding bits in the _GLOBAL_OVF_CTL.clr_ov field before beginning a new
sample interval.
U P G
ERIES NCORE ROGRAMMING UIDE
Table 2-16. B-Box Performance Monitoring MSRs
MSR Name
UNCORE PERFORMANCE MONITORING
MSR Size
Access
Address (bits)
RW_RW 0x0E4E 64
RW_RW 0x0E4D 64
RW_RW 0x0E46 64
RW_RW 0x0E45 64
RW_RW 0x0C77 64
RW_RW 0x0C76 64
RW_RW 0x0C75 64
RW_RW 0x0C74 64
RW_RW 0x0C73 64
RW_RW 0x0C72 64
RW_RW 0x0C71 64
RW_RW 0x0C70 64
RW_RW 0x0C62 32
RW_RW 0x0C61 32
RW_RW 0x0C60 32
RW_RW 0x0C37 64
RW_RW 0x0C36 64
RW_RW 0x0C35 64
RW_RW 0x0C34 64
RW_RW 0x0C33 64
RW_RW 0x0C32 64
RW_RW 0x0C31 64
RW_RW 0x0C30 64
RW_RW 0x0C22 32
RW_RW 0x0C21 32
RW_RW 0x0C20 32
Description
B-Box 1 PMON Mask Register
B-Box 1 PMON Match Register
B-Box 0 PMON Mask Register
B-Box 0 PMON Match Register
B-Box 1 PMON Counter 3
B-Box 1 PMON Event Select 3
B-Box 1 PMON Counter 2
B-Box 1 PMON Event Select 2
B-Box 1 PMON Counter 1
B-Box 1 PMON Event Select 1
B-Box 1 PMON Counter 0
B-Box 1 PMON Event Select 0
B-Box 1 PMON Global Overflow
Control
B-Box 1 PMON Global Status
B-Box 1 PMON Global Control
B-Box 0 PMON Counter 3
B-Box 0 PMON Event Select 3
B-Box 0 PMON Counter 2
B-Box 0 PMON Event Select 2
B-Box 0 PMON Counter 1
B-Box 0 PMON Event Select 1
B-Box 0 PMON Counter 0
B-Box 0 PMON Event Select 0
B-Box 0 PMON Global Overflow
Control
B-Box 0 PMON Global Status
B-Box 0 PMON Global Control
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