U-Box Performance Monitoring Events; U-Box Events Ordered By Code; Table 2-7. U_Msr_Pmon_Ctr Register - Field Definitions; Table 2-8. Performance Monitor Events For U-Box Events - Intel BX80571E7500 - Core 2 Duo 2.93 GHz Processor Programming Manual

I ® X ® P 7500 S
NTEL EON ROCESSOR
The U-Box performance monitor data register is 48b wide. A counter overflow occurs when a carry out
bit from bit 47 is detected. Software can force all uncore counting to freeze after N events by preloading
a monitor with a count value of 2
receipt of the PMI, the U-Box will disable counting (
During the interval of time between overflow and global disable, the counter value will wrap and
continue to collect events.
In this way, software can capture the precise number of events that occurred between the time uncore
counting was enabled and when it was disabled (or 'frozen') with minimal skew.
If accessible, software can continuously read the data registers without disabling event collection.
Field
event_count
2.2.2

U-Box Performance Monitoring Events

The set of events that can be monitored in the U-Box are summarized in the following section.
- Tracks NcMsgS packets generated by the U-Box, as they arbitrate to be broadcast. They are
prioritized as follows: Special Cycle->StopReq1/StartReq2->Lock/Unlock->Remote Interrupts->Local
Interrupts.
- Errors detected and distinguished between recoverable, corrected, uncorrected and fatal.
- Number of times cores were sent IPIs or were Woken up.
- Requests to the Ring or a B-Box.
etc.
2.2.3

U-Box Events Ordered By Code

Table 2-8 summarizes the directly-measured U-Box events.
BUF_VALID_LOCAL_INT
BUF_VALID_REMOTE_INT
BUF_VALID_LOCK
BUF_VALID_STST
BUF_VALID_SPC_CYCLES
U2R_REQUESTS
U2B_REQUEST_CYCLES
WOKEN
IPIS_SENT
RECOV
CORRECTED_ERR
U P
ERIES NCORE ROGRAMMING
- N and setting the control register to send a PMI to the U-Box. Upon
48
Table 2-7. U_MSR_PMON_CTR Register – Field Definitions
HW
Bits Reset
Val
47:0 0 48-bit performance event counter

Table 2-8. Performance Monitor Events for U-Box Events

Event
Symbol Name
Code
0x000
0x001
0x002
0x003
0x004
0x050
0x051
0x0F8
0x0F9
0x1DF
0x1E4
G
UIDE
Section 2.1.1.1, "Freezing on Counter
Description
Max
Inc/Cyc
1 Local IPI Buffer is valid
1 Remote IPI Buffer is valid
1 Lock Buffer is valid
1 Start/Stop Req Buffer is valid
1 SpcCyc Buffer is valid
1 Number U-Box to Ring Requests
1 U to B-Box Active Request Cycles
1 Number of core woken up
1 Number of core IPIs sent
1 Recoverable
1 Corrected Error
UNCORE PERFORMANCE MONITORING
Overflow").
Description
2-6