Uncore Performance Monitoring; Global Performance Monitoring Control; Counter Overflow; Freezing On Counter Overflow - Intel BX80571E7500 - Core 2 Duo 2.93 GHz Processor Programming Manual

I ® X ® P 7500 S
NTEL EON ROCESSOR
2.1

Global Performance Monitoring Control

2.1.1

Counter Overflow

If a counter overflows, it will send the overflow signal towards the U-Box. This signal will be
accumulated along the way in summary registers contained in each S-Box and a final summary register
in the U-Box.
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The Intel Xeon Processor 7500 Series uncore performance monitors may be configured to respond to
this overflow with two basic actions:
2.1.1.1

Freezing on Counter Overflow

Each uncore performance counter may be configured to, upon detection of overflow, disable (or
'freeze') all other counters in the uncore. To do so, the .pmi_en in the individual counter's control
register must be set to 1. If the U_MSR_PMON_GLOBAL_CTL.frz_all is also set to 1, once the U-Box
receives the PMI from the uncore box, it will set U_MSR_PMON_GLOBAL_CTL.en_all to 0 which will
disable all counting.
2.1.1.2

PMI on Counter Overflow

The uncore may also be configured to, upon detection of a performance counter overflow, send a PMI
signal to the core executing the monitoring software. To do so, the .pmi_en in the individual counter's
control register must be set to 1 and U_MSR_PMON_GLOBAL_CTL.pmi_core_sel must be set to point to
the core the monitoring software is executing on.
Note: PMI is decoupled from freeze, so if software also wants the counters frozen, it must set
U_MSR_PMON_GLOBAL_CTL.frz_all to 1.
2.1.2

Setting up a Monitoring Session

On HW reset, all the counters should be disabled. Enabling is hierarchical. So the following steps must
be taken to set up a new monitoring session:
a) Reset counters to ensure no stale values have been acquired from previous sessions:
- set U_MSR_PMON_GLOBAL_CTL.rst_all to 1.
b) Select event to monitor:
Determine what events should be captured and program the control registers to capture them (i.e.
typically selected by programming the .ev_sel bits although other bit fields may be involved).
i.e. Set B_MSR_PMON_EVT_SEL3.ev_sel to 0x03 to capture SNP_MERGE.
c) Enable counting locally:
i.e. Set B_MSR_PMON_EVT_SEL3.en to 1.
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ERIES NCORE ROGRAMMING UIDE

UNCORE PERFORMANCE MONITORING

UNCORE PERFORMANCE MONITORING
CHAPTER 2
2-1