B-Box Performance Monitoring; Overview Of The B-Box; B-Box Performance Monitoring Overview; B-Box Pmu - On Overflow And The Consequences (Pmi/Freeze) - Intel BX80571E7500 - Core 2 Duo 2.93 GHz Processor Programming Manual

I ® X ® P 7500 S
NTEL EON ROCESSOR
2.4

B-Box Performance Monitoring

2.4.1

Overview of the B-Box

The B-Box is responsible for the protocol side of memory interactions, including coherent and non-
coherent home agent protocols (as defined in the Intel
Additionally, the B-Box is responsible for ordering memory reads/writes to a given address such that
the M-Box does not have to perform this conflict checking. All requests for memory attached to the
coupled M-Box must first be ordered through the B-Box.
The B-Box has additional requirements on managing interactions with the M-Box, including RAS flows.
All requests in-flight in the M-Box are tracked in the B-Box. The primary function of the B-Box, is as the
coherent home agent for the Intel
algorithm requires the B-Box to track outstanding requests, log snoop responses and other control
messages, and make certain algorithmic decisions about how to respond to requests.
The B-Box only supports source snoopy Intel QuickPath Interconnect protocol flows.
2.4.2

B-Box Performance Monitoring Overview

Each of the two B-Boxes in the Intel Xeon Processor 7500 Series supports event monitoring through
four 48-bit wide counters (BBx_CR_B_MSR_PERF_CNT{3:0}). Each of these four counters is dedicated
to observe a specific set of events as specified in its control register
(BBx_CR_B_MSR_PERF_CTL{3:0}). The B-Box counters will increment by a maximum of 1 per cycle.
For information on how to setup a monitoring session, refer to
Monitoring Control".
2.4.2.1

B-Box PMU - On Overflow and the Consequences (PMI/Freeze)

If an overflow is detected from a B-Box performance counter, the overflow bit is set at the box level
(B_MSR_PMON_GLOBAL_STATUS.ov), and forwarded up the chain towards the U-Box. If a B-Box0
counter overflows, a notification is sent and stored in S-Box0 (S_MSR_PMON_SUMMARY.ov_mb) which,
in turn, sends the overflow notification up to the U-Box (U_MSR_PMON_GLOBAL_STATUS.ov_s0). If a
B-Box1 counter overflows, the overflow bit is set on the S-Box1 side of the hierarchy.
HW can be also configured (by setting the corresponding .pmi_en to 1) to send a PMI to the U-Box
when an overflow is detected. The U-Box may be configured to freeze all uncore counting and/or send a
PMI to selected cores when it receives this signal.
Once a freeze has occurred, in order to see a new freeze, the overflow field responsible for the freeze,
found in B_MSR_PMON_GLOBAL_OVF_CTL.clr_ov, must be cleared. Assuming all the counters have
been locally enabled (.en bit in data registers meant to monitor events) and the overflow bit(s) has
been cleared, the B-Box is prepared for a new sample interval. Once the global controls have been re-
enabled (Section 2.1.4, "Enabling a New Sample Interval from Frozen
U P G
ERIES NCORE ROGRAMMING UIDE
®
QuickPath Interconnect cache coherence protocol. The home agent
UNCORE PERFORMANCE MONITORING
®
QuickPath Interconnect Specification).
Section 2.1, "Global Performance
Counters") counting will resume.
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