Table 2-98. W_Msr_Pmon_Evt_Sel_{3-0} Register - Field Definitions; Table 2-99. W_Msr_Pmon_Fixed_Ctr_Ctl Register - Field Definitions - Intel BX80571E7500 - Core 2 Duo 2.93 GHz Processor Programming Manual

I ® X ® P 7500 S
NTEL EON ROCESSOR
Table 2-98. W_MSR_PMON_EVT_SEL_{3-0} Register – Field Definitions
Field
ig
rsv
ig
rsv
ig
thresh
invert
en
ig
pmi_en
ig
edge_detect
ig
umask
ev_sel
Table 2-99. W_MSR_PMON_FIXED_CTR_CTL Register – Field Definitions
Field
ig
rsv
pmi_en
en
The W-Box performance monitor data registers are 48b wide. A counter overflow occurs when a carry
out bit from bit 47 is detected. Software can force all uncore counting to freeze after N events by
preloading a monitor with a count value of (2
the U-Box. Upon receipt of the PMI, the U-Box will disable counting (
Counter Overflow"). During the interval of time between overflow and global disable, the counter value
will wrap and continue to collect events.
In this way, software can capture the precise number of events that occurred between the time uncore
counting was enabled and when it was disabled (or 'frozen') with minimal skew.
If accessible, software can continuously read the data registers without disabling event collection.
U P G
ERIES NCORE ROGRAMMING UIDE
HW
Bits Reset
Val
63 0 Read zero; writes ignored. (?)
62:61 0 Reserved; Must write to 0 else behavior is undefined.
60:51 0 Read zero; writes ignored. (?)
50 0 Reserved; Must write to 0 else behavior is undefined.
49:32 0 Read zero; writes ignored. (?)
31:24 0 Threshold used for counter comparison.
23 0 Invert threshold comparison. When '0', the comparison will be thresh >=
event. When '1', the comparison will be threshold < event.
22 0 Counter enable
21 0 Read zero; writes ignored. (?)
20 0 PMI Enable. If bit is set, when corresponding counter overflows, a PMI
exception is sent to the U-Box.
17:16 0 Read zero; writes ignored. (?)
18 0 Edge Detect. When bit is set, 0->1 transition of a one bit event input will
cause counter to increment. When bit is 0, counter will increment for
however long event is asserted.
17:16 0 Read zero; writes ignored. (?)
15:8 0 In W-Box, this field is used to enable core scope events per core. Bit 0
masks Core 0, bit 1 masks Core 1, etc.
7:0 0 Event Select
HW
Bits Reset
Val
63:3 0 Read zero; writes ignored. (?)
2 0 Reserved; Must write to 0 else behavior is undefined.
1 0 PMI Enable. If bit is set, when corresponding counter overflows, a PMI
exception is sent to the U-Box.
0 0 Counter enable
- 1) - N and setting the control register to send a PMI to
48
UNCORE PERFORMANCE MONITORING
Description
Description
Section 2.1.1.1, "Freezing on
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