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Intel BX80613I7980 Datasheet

Intel core i7-900 desktop processor extreme edition series and intel core i7-900 desktop processor series on 32-nm process
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®
Intel
Core™ i7-900 Desktop
Processor Extreme Edition Series
®
and Intel
Core™ i7-900 Desktop
Processor Series on 32-nm Process
Datasheet, Volume 1
June 2011
Document # 323252-003

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Summary of Contents for Intel BX80613I7980

  • Page 1 ® Intel Core™ i7-900 Desktop Processor Extreme Edition Series ® and Intel Core™ i7-900 Desktop Processor Series on 32-nm Process Datasheet, Volume 1 June 2011 Document # 323252-003...
  • Page 2 Intel Turbo Boost Technology. For more information, see www.intel.com. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Intel, Intel SpeedStep, Intel Core, and the Intel logo are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States and other countries.

  • Page 3: Table Of Contents

    Introduction ......................9 Terminology ..................... 10 References ....................... 11 Electrical Specifications ................... 13 ® ® Intel QuickPath Interconnect (Intel QPI) Differential Signaling......13 Power and Ground Lands..................13 Decoupling Guidelines ..................13 2.3.1 Decoupling ............. 14 Processor Clocking (BCLK_DP, BCLK_DN) ............. 14 2.4.1...
  • Page 4 7.2.2.2 Package C1/C1E State ...............91 7.2.2.3 Package C3 State ..............91 7.2.2.4 Package C6 State ..............92 Sleep States .....................92 ® ACPI P-States (Intel Turbo Boost Technology) .............92 ® Enhanced Intel SpeedStep Technology ...............93 Boxed Processor Specifications................95 Introduction ......................95 Mechanical Specifications ..................96 8.2.1...
  • Page 5 Processor Package Drawing (Sheet 2 of 2) ............37 Processor Top-side Markings ................39 Processor Land Coordinates and Quadrants, Top View ..........40 ® Intel Core™ i7-900 Desktop Processor Extreme Edition Series Thermal Profile ..77 ® Intel Core™ i7-900 Desktop Processor Series Thermal Profile ........ 78 Thermal Test Vehicle (TTV) Case Temperature (T ) Measurement Location ...
  • Page 6 2-17 Intel QuickPath Interconnect (Intel QPI) Specifications .........32 ® 2-18 Parameter Values for Intel QuickPath Interconnect (Intel QPI) Channel at 6.4 GT/s ..33 Processor Loading Specifications ................38 Package Handling Guidelines ................38 Processor Materials ....................39 Land Listing by Land Name .................41 Land Listing by Land Number ................56...

  • Page 7: Revision History

    Revision History Revision Description Date Number • Initial release March 2010 ® • Added Intel Core™ i7-970 desktop processor series July 2010 ® • Added Intel Core™ i7-990X desktop processor Extreme Edition June 2011 ® • Added Intel Core™ i7-980 desktop processor §...
  • Page 8 Datasheet, Volume 1...

  • Page 9: Introduction

    The processor is a multi-core processor built on the 32-nm process technology, that uses up to 130 W thermal design power (TDP). The processor features an Intel QPI point-to-point link capable of up to 6.4 GT/s, 12 MB Level 3 cache, and an integrated memory controller.

  • Page 10: Terminology

    Refer to http://developer.intel.com/ for future reference on up to date nomenclatures. ® • Intel 64 Architecture — An enhancement to the Intel IA-32 architecture, allowing the processor to execute operating systems and applications written to Datasheet, Volume 1...

  • Page 11: References

    Introduction take advantage of Intel 64. Further details on the Intel 64 architecture and programming model can be found at http://developer.intel.com/technology/intel64/. ® ® • Intel Virtualization Technology (Intel VT) — A set of hardware enhancements to Intel server and client platforms that can improve virtualization ®...
  • Page 12 Introduction § Datasheet, Volume 1...

  • Page 13: Electrical Specifications

    QPI) Differential Signaling The processor provides an Intel QPI port for high speed serial transfer between other Intel QPI-enabled components. The Intel QPI port consists of two unidirectional links (for transmit and receive). Intel QPI uses a differential signalling scheme where pairs of opposite-polarity (D_P, D_N) signals are used.

  • Page 14: Processor Clocking (Bclk_Dp, Bclk_Dn)

    The processor core, Intel QPI, and integrated memory controller frequencies are generated from BCLK_DP and BCLK_DN. Unlike previous processors based on front side bus architecture, there is no direct link between core frequency and Intel QPI link frequency (such as, no core frequency to Intel QPI multiplier). The processor maximum core frequency, Intel QPI link frequency and integrated memory controller frequency, are set during manufacturing.

  • Page 15: Voltage Identification (Vid)

    Electrical Specifications Voltage Identification (VID) The Voltage Identification (VID) specification for the processor is defined by the Voltage Regulator Down (VRD) 11.1 Design Guidelines. The voltage set by the VID signals is the reference voltage regulator output voltage to be delivered to the processor VCC pins.

  • Page 16: Voltage Identification Definition

    Electrical Specifications Table 2-1. Voltage Identification Definition (Sheet 1 of 2) CC_MAX CC_MAX 1.04375 1.03750 1.60000 1.03125 1.59375 1.02500 1.58750 1.01875 1.58125 1.01250 1.57500 1.00625 1.56875 1.00000 1.56250 0.99375 1.55625 0.98750 1.55000 0.98125 1.54375 0.97500 1.53750 0.96875 1.53125 0.96250 1.52500 0.95626 1.51875 0.95000...
  • Page 17 Electrical Specifications Table 2-1. Voltage Identification Definition (Sheet 2 of 2) CC_MAX CC_MAX 1.31250 0.74375 1.30625 0.73750 1.30000 0.73125 1.29375 0.72500 1.28750 0.71875 1.28125 0.71250 1.27500 0.70625 1.26875 0.70000 1.26250 0.69375 1.25625 0.68750 1.25000 0.68125 1.24375 0.67500 1.23750 0.66875 1.23125 0.66250 1.22500 0.65625...

  • Page 18: Reserved Or Unused Signals

    Reserved Reserved Reserved Reserved Reserved Reserved ® Intel Core™ i7-900 desktop processor Extreme Edition series and ® Intel Core™ i7-900 desktop processor series on 32-nm process Reserved Notes: 1. The MSID[2:0] signals are provided to indicate the market segment for the processor and may be used for future processor compatibility or for keying.

  • Page 19: Signal Groups

    Table 2-3. Signal Groups (Sheet 1 of 2) Signal Group Type Signals System Reference Clock Differential Clock Input BCLK_DP, BCLK_DN Intel QPI Signal Groups QPI_DRX_D[N/P][19:0], QPI_CLKRX_DP, Differential Intel QPI Input QPI_CLKRX_DN QPI_DTX_D[N/P][19:0], QPI_CLKTX_DP, Differential Intel QPI Output QPI_CLKTX_DN DDR3 Reference Clocks...

  • Page 20: Test Access Port (Tap) Connection

    Electrical Specifications Table 2-3. Signal Groups (Sheet 2 of 2) Signal Group Type Signals Single ended CMOS Output VTT_VID[4:2] Single ended Analog Input ISENSE Reset Signal Single ended Reset Input RESET# PWRGOOD Signals Single ended Asynchronous Input VCCPWRGOOD, VTTPWRGOOD, VDDPWRGOOD Power/Other Power VCC, VTTA, VTTD, VCCPLL, VDDQ...

  • Page 21: Platform Environmental Control Interface (Peci) Dc Specifications

    Platform Environmental Control Interface (PECI) DC Specifications PECI is an Intel proprietary interface that provides a communication channel between Intel processors and chipset components to external thermal monitoring devices. The processor contains a Digital Thermal Sensor (DTS) that reports a relative die temperature as an offset from Thermal Control Circuit (TCC) activation temperature.

  • Page 22: Input Device Hysteresis

    Electrical Specifications 2.9.2 Input Device Hysteresis The input buffers in both client and host models must use a Schmitt-triggered input design for improved noise immunity. Use Figure 2-2 as a guide for input buffer design. Figure 2-2. Input Device Hysteresis Maximum V PECI High Range Minimum V...

  • Page 23: Processor Dc Specifications

    Electrical Specifications Table 2-6. Processor Absolute Minimum and Maximum Ratings 1, 2 Symbol Parameter Unit Notes Processor Core voltage with respect to V -0.3 Voltage for the analog portion of the integrated memory controller, QPI link and Shared Cache -0.3 with respect to V Voltage for the digital portion of the integrated memory controller, QPI link and Shared Cache...

  • Page 24: Dc Voltage And Current Specification

    VID range. Note that this differs from the VID employed by the processor during a power management event (Adaptive Thermal ® Monitor, Enhanced Intel SpeedStep Technology, or Low Power States). The voltage specification requirements are measured across VCC_SENSE and VSS_SENSE lands at the socket with a 100 MHz bandwidth oscilloscope, 1.5 pF maximum probe capacitance, and 1 M...

  • Page 25: Vcc

    Electrical Specifications Table 2-8. Static and Transient Tolerance Notes CC_Max CC_Typ CC_Min VID – 0.000 VID – 0.019 VID – 0.038 1, 2, 3 VID – 0.004 VID – 0.023 VID – 0.042 1, 2, 3 VID – 0.008 VID – 0.027 VID –...

  • Page 26: Vcc

    Electrical Specifications Figure 2-3. Static and Transient Tolerance Load Lines Icc [A] VID - 0.000 VID - 0.013 VID - 0.025 Vcc Maximum VID - 0.038 VID - 0.050 VID - 0.063 VID - 0.075 Vcc Typical VID - 0.088 VID - 0.100 VID - 0.113 Vcc Minimum...
  • Page 27 Electrical Specifications Table 2-10. V Static and Transient Tolerance Notes TT_Max TT_Typ TT_Min VID + 0.0315 VID – 0.0000 VID – 0.0315 VID + 0.0255 VID – 0.0060 VID – 0.0375 VID + 0.0195 VID – 0.0120 VID – 0.0435 VID + 0.0135 VID –...

  • Page 28: Vtt Static And Transient Tolerance Load Line

    Electrical Specifications Figure 2-4. Static and Transient Tolerance Load Line Itt [A] (sum of Itta and Ittd) 0.0500 0.0375 0.0250 0.0125 0.0000 -0.0125 Vtt Maximum -0.0250 -0.0375 -0.0500 -0.0625 -0.0750 Vtt Typical -0.0875 -0.1000 -0.1125 -0.1250 Vtt Minimum -0.1375 -0.1500 -0.1625 -0.1750 -0.1875...

  • Page 29: Reset# Signal Dc Specifications

    Electrical Specifications is defined as the minimum voltage level at a receiving agent that will be interpreted as a logical high value. and V may experience excursions above V . However, input signal drivers must comply with the signal quality specifications. COMP resistance must be provided on the system board with 1% resistors.

  • Page 30: Pwrgood Signal Group Dc Specifications

    Electrical Specifications Table 2-14. PWRGOOD Signal Group DC Specifications Symbol Parameter Units Notes Input Low Voltage for VCCPWRGOOD and VTTPWRGOOD — — 0.25 * V Signals Input Low Voltage for — — 0.29 VDDPWRGOOD Signal Input High Voltage for VCCPWRGOOD and VTTPWRGOOD 0.75 * V —...

  • Page 31: Vcc Overshoot Specification

    Electrical Specifications 2.11.2 Overshoot Specification The processor can tolerate short transient overshoot events where V exceeds the VID voltage when transitioning from a high-to-low current load condition. This overshoot cannot exceed VID + V is the maximum allowable overshoot above OS_MAX OS_MAX VID).

  • Page 32: Intel ® Quickpath Interconnect (Intel ® Qpi) Specifications

    QPI) Specifications The processor Intel QPI specifications in this section are defined at the processor pins. Routing topologies are dependent on the processors supported and the chipset used in the design. In most cases, termination resistors are not required as these are integrated into the processor silicon.

  • Page 33: Parameter Values For Intel

    Electrical Specifications ® ® Table 2-18. Parameter Values for Intel QuickPath Interconnect (Intel QPI) Channel at 6.4 GT/s Parameter Symbol Unit Notes DC resistance of Tx terminations at half the single ended swing (which is usually 0.25*V — ohms TX_LOW_CM_DC...
  • Page 34 Electrical Specifications Datasheet, Volume 1...

  • Page 35: Package Mechanical Specifications

    Package Mechanical Specifications Package Mechanical Specifications The processor is packaged in a Flip-Chip Land Grid Array package that interfaces with the motherboard using an LGA1366 socket. The package consists of a processor mounted on a substrate land-carrier. An integrated heat spreader (IHS) is attached to the package substrate and core and serves as the mating surface for processor thermal solutions, such as a heatsink.

  • Page 36: Processor Package Drawing (Sheet 1 Of 2)

    Package Mechanical Specifications Figure 3-2. Processor Package Drawing (Sheet 1 of 2) Datasheet, Volume 1...

  • Page 37: Processor Package Drawing (Sheet 2 Of 2)

    Package Mechanical Specifications Figure 3-3. Processor Package Drawing (Sheet 2 of 2) Datasheet, Volume 1...

  • Page 38: Processor Component Keep-Out Zones

    Package Mechanical Specifications Processor Component Keep-Out Zones The processor may contain components on the substrate that define component keep- out zone requirements. A thermal and mechanical solution design must not intrude into the required keep-out zones. Decoupling capacitors are typically mounted to either the top-side or land-side of the package substrate.

  • Page 39: Processor Mass Specification

    Gold Plated Copper Processor Markings Figure 3-4 shows the top-side markings on the processor. This diagram is to aid in the identification of the processor. Figure 3-4. Processor Top-side Markings INTEL ©'07 PROC# BRAND SLxxx [COO] SPEED/CACHE/INTC/FMB [FPO] Datasheet, Volume 1...

  • Page 40: Processor Land Coordinates

    Package Mechanical Specifications Processor Land Coordinates Figure 3-5 shows the top view of the processor land coordinates. The coordinates are referred to throughout the document to identify processor lands. Figure 3-5. Processor Land Coordinates and Quadrants, Top View § Datasheet, Volume 1...

  • Page 41: Land Listing

    Land Listing Land Listing This chapter provides sorted land lists in Table 4-1 Table 4-2. Table 4-1 is a listing of all processor lands ordered alphabetically by land name. Table 4-2 is a listing of all processor lands ordered by land number. Table 4-1.
  • Page 42 Land Listing Table 4-1. Land Listing by Land Name Table 4-1. Land Listing by Land Name (Sheet 3 of 29) (Sheet 4 of 29) Land Buffer Land Buffer Land Name Direction Land Name Direction Type Type DDR0_DQ[38] CMOS DDR0_MA[14] CMOS DDR0_DQ[39] CMOS DDR0_MA[15]...
  • Page 43 Land Listing Table 4-1. Land Listing by Land Name Table 4-1. Land Listing by Land Name (Sheet 5 of 29) (Sheet 6 of 29) Land Buffer Land Buffer Land Name Direction Land Name Direction Type Type DDR1_DQ[11] CMOS DDR1_DQ[59] CMOS DDR1_DQ[12] CMOS DDR1_DQ[60]...
  • Page 44 Land Listing Table 4-1. Land Listing by Land Name Table 4-1. Land Listing by Land Name (Sheet 7 of 29) (Sheet 8 of 29) Land Buffer Land Buffer Land Name Direction Land Name Direction Type Type DDR2_CKE[0] CMOS DDR2_DQ[32] CMOS DDR2_CKE[1] CMOS DDR2_DQ[33]...
  • Page 45 Land Listing Table 4-1. Land Listing by Land Name Table 4-1. Land Listing by Land Name (Sheet 9 of 29) (Sheet 10 of 29) Land Buffer Land Buffer Land Name Direction Land Name Direction Type Type DDR2_MA[0] CMOS QPI_DRX_DN[13] AN42 DDR2_MA[1] CMOS QPI_DRX_DN[14]...
  • Page 46 Land Listing Table 4-1. Land Listing by Land Name Table 4-1. Land Listing by Land Name (Sheet 11 of 29) (Sheet 12 of 29) Land Buffer Land Buffer Land Name Direction Land Name Direction Type Type QPI_DTX_DP[1] AF39 RSVD QPI_DTX_DP[2] AK37 RSVD QPI_DTX_DP[3]...
  • Page 47 Land Listing Table 4-1. Land Listing by Land Name Table 4-1. Land Listing by Land Name (Sheet 13 of 29) (Sheet 14 of 29) Land Buffer Land Buffer Land Name Direction Land Name Direction Type Type RSVD RSVD RSVD RSVD RSVD AA40 RSVD...
  • Page 48 Land Listing Table 4-1. Land Listing by Land Name Table 4-1. Land Listing by Land Name (Sheet 15 of 29) (Sheet 16 of 29) Land Buffer Land Buffer Land Name Direction Land Name Direction Type Type RSVD RSVD AW41 RSVD AM36 RSVD AW42...
  • Page 49 Land Listing Table 4-1. Land Listing by Land Name Table 4-1. Land Listing by Land Name (Sheet 17 of 29) (Sheet 18 of 29) Land Buffer Land Buffer Land Name Direction Land Name Direction Type Type AJ33 AN15 AK11 AN16 AK12 AN18 AK13...
  • Page 50 Land Listing Table 4-1. Land Listing by Land Name Table 4-1. Land Listing by Land Name (Sheet 19 of 29) (Sheet 20 of 29) Land Buffer Land Buffer Land Name Direction Land Name Direction Type Type AT16 AW12 AT18 AW13 AT19 AW15 AT21...
  • Page 51 Land Listing Table 4-1. Land Listing by Land Name Table 4-1. Land Listing by Land Name (Sheet 21 of 29) (Sheet 22 of 29) Land Buffer Land Buffer Land Name Direction Land Name Direction Type Type VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ...
  • Page 52 Land Listing Table 4-1. Land Listing by Land Name Table 4-1. Land Listing by Land Name (Sheet 23 of 29) (Sheet 24 of 29) Land Buffer Land Buffer Land Name Direction Land Name Direction Type Type AD37 AL32 AD41 AL35 AD43 AL36 AL37...
  • Page 53 Land Listing Table 4-1. Land Listing by Land Name Table 4-1. Land Listing by Land Name (Sheet 25 of 29) (Sheet 26 of 29) Land Buffer Land Buffer Land Name Direction Land Name Direction Type Type AP43 AV22 AV23 AV26 AR11 AV29 AR14...
  • Page 54 Land Listing Table 4-1. Land Listing by Land Name Table 4-1. Land Listing by Land Name (Sheet 27 of 29) (Sheet 28 of 29) Land Buffer Land Buffer Land Name Direction Land Name Direction Type Type Datasheet, Volume 1...
  • Page 55 Land Listing Table 4-1. Land Listing by Land Name (Sheet 29 of 29) Land Buffer Land Name Direction Type VSS_SENSE Analog VSS_SENSE_VTT AE37 Analog VTT_SENSE AE36 Analog VTT_VID2 CMOS VTT_VID3 CMOS VTT_VID4 CMOS VTTA AD10 VTTA AE10 VTTA AE11 VTTA AE33 VTTA AF11...

  • Page 56: Land Listing By Land Number

    Land Listing Table 4-2. Land Listing by Land Number Table 4-2. Land Listing by Land Number (Sheet 2 of 29) (Sheet 1 of 29) Land Buffer Land Buffer Pin Name Direction Pin Name Direction Type Type DDR0_MA[1] CMOS VDDQ BPM#[1] DDR0_MA[4] CMOS DDR0_MA[5]...
  • Page 57 Land Listing Table 4-2. Land Listing by Land Number Table 4-2. Land Listing by Land Number (Sheet 3 of 29) (Sheet 4 of 29) Land Buffer Land Buffer Pin Name Direction Pin Name Direction Type Type BA36 QPI_DRX_DP[4] BPM#[6] BA37 QPI_DRX_DN[4] BA38 QPI_DRX_DP[6]...
  • Page 58 Land Listing Table 4-2. Land Listing by Land Number Table 4-2. Land Listing by Land Number (Sheet 5 of 29) (Sheet 6 of 29) Land Buffer Land Buffer Pin Name Direction Pin Name Direction Type Type DDR1_DQS_P[4] CMOS DDR0_ODT[0] CMOS DDR1_DQ[33] CMOS DDR2_ODT[1]...
  • Page 59 Land Listing Table 4-2. Land Listing by Land Number Table 4-2. Land Listing by Land Number (Sheet 7 of 29) (Sheet 8 of 29) Land Buffer Land Buffer Pin Name Direction Pin Name Direction Type Type VDDQ DDR2_MA[9] CMOS DDR2_MA[2] CMOS DDR2_MA[11] CMOS...
  • Page 60 Land Listing Table 4-2. Land Listing by Land Number Table 4-2. Land Listing by Land Number (Sheet 9 of 29) (Sheet 10 of 29) Land Buffer Land Buffer Pin Name Direction Pin Name Direction Type Type DDR1_MA[6] CMOS DDR1_DQ[26] CMOS VDDQ RSVD RSVD...
  • Page 61 Land Listing Table 4-2. Land Listing by Land Number Table 4-2. Land Listing by Land Number (Sheet 11 of 29) (Sheet 12 of 29) Land Buffer Land Buffer Pin Name Direction Pin Name Direction Type Type RSVD RSVD RSVD DDR0_DQ[48] CMOS DDR2_DQ[22] CMOS...
  • Page 62 Land Listing Table 4-2. Land Listing by Land Number Table 4-2. Land Listing by Land Number (Sheet 13 of 29) (Sheet 14 of 29) Land Buffer Land Buffer Pin Name Direction Pin Name Direction Type Type DDR0_DQS_N[6] CMOS DDR0_DQ[54] CMOS DDR2_DQS_P[7] CMOS DDR1_DQ[50]...
  • Page 63 Land Listing Table 4-2. Land Listing by Land Number Table 4-2. Land Listing by Land Number (Sheet 15 of 29) (Sheet 16 of 29) Land Buffer Land Buffer Pin Name Direction Pin Name Direction Type Type AA40 RSVD VCCPLL AA41 RSVD DDR2_DQ[0] CMOS...
  • Page 64 Land Listing Table 4-2. Land Listing by Land Number Table 4-2. Land Listing by Land Number (Sheet 17 of 29) (Sheet 18 of 29) Land Buffer Land Buffer Pin Name Direction Pin Name Direction Type Type RSVD VTT_VID3 CMOS RSVD VTTD RSVD VTTD...
  • Page 65 Land Listing Table 4-2. Land Listing by Land Number Table 4-2. Land Listing by Land Number (Sheet 19 of 29) (Sheet 20 of 29) Land Buffer Land Buffer Pin Name Direction Pin Name Direction Type Type AH34 AK17 AH35 BCLK_DN CMOS AK18 AH36...
  • Page 66 Land Listing Table 4-2. Land Listing by Land Number Table 4-2. Land Listing by Land Number (Sheet 21 of 29) (Sheet 22 of 29) Land Buffer Land Buffer Pin Name Direction Pin Name Direction Type Type AL22 AM27 AL23 AM28 AL24 AM29 AL25...
  • Page 67 Land Listing Table 4-2. Land Listing by Land Number Table 4-2. Land Listing by Land Number (Sheet 23 of 29) (Sheet 24 of 29) Land Buffer Land Buffer Pin Name Direction Pin Name Direction Type Type AN32 AP37 AN33 AP38 QPI_DRX_DP[19] AN34 AP39...
  • Page 68 Land Listing Table 4-2. Land Listing by Land Number Table 4-2. Land Listing by Land Number (Sheet 25 of 29) (Sheet 26 of 29) Land Buffer Land Buffer Pin Name Direction Pin Name Direction Type Type AR42 QPI_CLKRX_DN RSVD AR43 QPI_DRX_DN[11] RSVD RSVD...
  • Page 69 Land Listing Table 4-2. Land Listing by Land Number Table 4-2. Land Listing by Land Number (Sheet 27 of 29) (Sheet 28 of 29) Land Buffer Land Buffer Pin Name Direction Pin Name Direction Type Type AW14 AV10 AW15 AV11 AW16 AV12 AW17...
  • Page 70 Land Listing Table 4-2. Land Listing by Land Number (Sheet 29 of 29) Land Buffer Pin Name Direction Type AY21 AY22 AY23 AY24 AY25 AY26 AY27 AY28 AY29 AY30 AY31 AY32 AY33 AY34 AY35 RSVD AY36 QPI_DRX_DN[3] AY37 AY38 QPI_DRX_DN[6] AY39 RSVD AY40...

  • Page 71: Signal Descriptions

    Impedance compensation must be terminated on the system COMP0 board using a precision resistor. QPI_CLKRX_DN Intel QPI received clock is the input clock that corresponds to the received data. QPI_CLKRX_DP QPI_CLKTX_DN Intel QPI forwarded clock sent with the outbound data.
  • Page 72 Signal Descriptions Table 5-1. Signal Definitions (Sheet 2 of 4) Name Type Description Notes Differential pair, Data Strobe x8. Differential strobes latch data/ECC for each DRAM. Different numbers of strobes are DDR{0/1/2}_DQS_N[7:0] used depending on whether the connected DRAMs are x4 or DDR{0/1/2}_DQS_P[7:0] x8.
  • Page 73 Signal Descriptions Table 5-1. Signal Definitions (Sheet 3 of 4) Name Type Description Notes TDI (Test Data In) transfers serial test data into the processor. TDI provides the serial input needed for JTAG specification support. TDO (Test Data Out) transfers serial test data out of the processor.
  • Page 74 Signal Descriptions Table 5-1. Signal Definitions (Sheet 4 of 4) Name Type Description Notes VID[7:0] (Voltage ID) are used to support automatic selection of power supply voltages (V ). Refer to the Voltage Regulator-Down (VRD) 11.1 Design Guidelines for more information.

  • Page 75: Thermal Specifications

    The fan speed control algorithm can be updated to use the additional information to optimize acoustics. To allow the optimal operation and long-term reliability of Intel processor-based systems, the processor thermal solution must deliver the specified thermal solution performance in response to the DTS sensor value.

  • Page 76: Processor Thermal Specifications

    AMBIENT Processor idle power is specified under the lowest possible idle state: processor package C6 state. Achieving processor package C6 state is not supported by all chipsets. See the Intel X58 Express Chipset Datasheet for more details. Datasheet, Volume 1...

  • Page 77: Intel ® Core™ I7-900 Desktop Processor Extreme Edition Series Thermal Profile

    Thermal Specifications ® Figure 6-1. Intel Core™ i7-900 Desktop Processor Extreme Edition Series Thermal Profile 70.0 y = 43.2 + 0.19 * P 65.0 60.0 55.0 50.0 45.0 40.0 TTV Power (W) Notes: Refer to Table 6-2 for discrete points that constitute the thermal profile.

  • Page 78: Intel ® Core™ I7-900 Desktop Processor Series Thermal Profile

    Thermal Specifications ® Figure 6-2. Intel Core™ i7-900 Desktop Processor Series Thermal Profile Notes: Refer to Table 6-3 for discrete points that constitute the thermal profile. Refer to the appropriate processor Thermal and Mechanical Design Guidelines (see Section 1.2) for system and environmental implementation details.

  • Page 79: Specification For Operation Where Digital Thermal Sensor Exceeds Tcontrol

    Thermal Specifications 6.1.1.1 Specification for Operation Where Digital Thermal Sensor Exceeds CONTROL When the DTS value is less than T , the fan speed control algorithm can reduce CONTROL the speed of the thermal solution fan. This remains the same as with the previous guidance for fan speed control.

  • Page 80: Thermal Metrology

    Thermal Specifications 6.1.2 Thermal Metrology The minimum and maximum TTV case temperatures (T ) are specified in Table 6-1, CASE Table 6-2 and are measured at the geometric top center of the thermal test vehicle integrated heat spreader (IHS). Figure 6-3 illustrates the location where T CASE temperature measurements should be made.

  • Page 81: Processor Thermal Features

    Thermal Specifications Processor Thermal Features 6.2.1 Processor Temperature The processor contains a software readable field in the IA32_TEMPERATURE_TARGET register that contains the minimum temperature at which the TCC will be activated and PROCHOT# will be asserted. The TCC activation temperature is calibrated on a part-by- part basis and normal factory variation may result in the actual TCC activation temperature being higher than the value listed in the register.

  • Page 82: Frequency/Vid Control

    Thermal Specifications 6.2.2.1 Frequency/VID Control When the Digital Temperature Sensor (DTS) reaches a value of 0 (DTS temperatures reported using PECI may not equal zero when PROCHOT# is activated, see Section 6.3 for further details), the TCC will be activated and the PROCHOT# signal will be asserted.

  • Page 83: Clock Modulation

    Unless immediate action is taken to resolve the failure, the processor will probably reach the Thermtrip temperature (see Section 6.2.3 ) within a short time. To prevent possible permanent silicon damage, Intel recommends removing power from the processor within ½ second of the Critical Temperature Flag being set. 6.2.2.5 PROCHOT# Signal An external signal, PROCHOT# (processor hot), is asserted when the processor core temperature has exceeded its specification.

  • Page 84: Thermtrip# Signal

    Introduction The Platform Environment Control Interface (PECI) is a one-wire interface that provides a communication channel between the Intel processor and chipset components to external monitoring devices. The processor implements a PECI interface to allow communication of processor thermal and other information to other devices on the platform.

  • Page 85: Fan Speed Control With Digital Thermal Sensor

    Thermal Specifications 6.3.1.1 Fan Speed Control with Digital Thermal Sensor Fan speed control solutions use a value stored in the static variable, T . The DTS CONTROL temperature data that is delivered over PECI (in response to a GetTemp0() command), is compared to this T reference.

  • Page 86: Peci Specifications

    Thermal Specifications 6.3.2 PECI Specifications 6.3.2.1 PECI Device Address The PECI register resides at address 30h. 6.3.2.2 PECI Command Support The processor supports the PECI commands listed in Table 6-5. Table 6-5. Supported PECI Command Functions and Codes Command Code Comments Function This command targets a valid PECI device address followed by zero Write...

  • Page 87: Storage Conditions Specifications

    For functional operation, refer to the processor case temperature specifications. These ratings apply to the Intel component and do not include the tray or packaging. Failure to adhere to this specification can affect the long-term reliability of the processor.
  • Page 88 Thermal Specifications Datasheet, Volume 1...

  • Page 89: Features

    Chapter 2. Note that request to execute BIST is not selected by hardware but is passed across the Intel QPI link during initialization. The sampled information configures the processor for subsequent operation. These configuration options cannot be changed except by another reset. All resets reconfigure the processor;...

  • Page 90: Thread And Core Power State Descriptions

    A System Management Interrupt (SMI) handler will return execution to either Normal ® state or the C1 state. See the Intel 64 and IA-32 Architecture Software Developer's Manuals, Volume III: System Programmer's Guide for more information. While in C1/C1E state, the processor will process bus snoops and snoops from the other threads.

  • Page 91: C3 State

    C3 but other component(s) in the system have only granted permission to enter C3. If Intel QPI L1 has been granted, the processor will disable some clocks and PLLs and for processors with an integrated memory controller, the DRAM will be put into self- refresh.

  • Page 92: Package C6 State

    C6 but the other component(s) have only granted permission to enter C6. If Intel QPI L1 has been granted, the processor will disable some clocks and PLLs and the shared cache will enter a deep sleep state. Additionally, for processors with an integrated memory controller, the DRAM will be put into self-refresh.

  • Page 93: Enhanced Intel Speedstep Technology

    Features ® Enhanced Intel SpeedStep Technology The processor features Enhanced Intel SpeedStep Technology. Following are the key features of Enhanced Intel SpeedStep Technology: • Multiple voltage and frequency operating points provide optimal performance at the lowest power. • Voltage and frequency selection is software controlled by writing to processor MSRs: —...
  • Page 94 Features Datasheet, Volume 1...

  • Page 95: Boxed Processor Specifications

    Boxed Processor Specifications Introduction The processor will also be offered as an Intel boxed processor. Intel boxed processors are intended for system integrators who build systems from baseboards and standard components. The boxed processor will be supplied with a cooling solution. This chapter documents baseboard and system requirements for the cooling solution that will be supplied with the boxed processor.

  • Page 96: Mechanical Specifications

    Boxed Processor Specifications Mechanical Specifications 8.2.1 Boxed Processor Cooling Solution Dimensions This section covers the mechanical specifications of the boxed processor. The boxed processor will be shipped with an unattached fan heatsink. Figure 8-1 shows a mechanical representation of the boxed processor. Clearance is required around the fan heatsink to ensure unimpeded airflow for proper cooling.

  • Page 97: Space Requirements For The Boxed Processor (Top View)

    Boxed Processor Specifications Figure 8-3. Space Requirements for the Boxed Processor (top view) Notes: Diagram does not show the attached hardware for the clip design and is provided only as a mechanical representation. Figure 8-4. Space Requirements for the Boxed Processor (overall view) Datasheet, Volume 1...

  • Page 98: Boxed Processor Fan Heatsink Weight

    Boxed Processor Specifications 8.2.2 Boxed Processor Fan Heatsink Weight The boxed processor fan heatsink will not weigh more than 550 grams. See Chapter 6 and the appropriate processor Thermal and Mechanical Design Guidelines (see Section 1.2) for details on the processor weight and heatsink requirements. 8.2.3 Boxed Processor Retention Mechanism and Heatsink Attach Clip Assembly...

  • Page 99: Thermal Specifications

    Boxed Processor Specifications Table 8-1. Fan Heatsink Power and Signal Specifications Description Unit Notes +12 V: 12 volt fan power supply 10.8 13.2 - Peak steady-state fan current draw — — - Average steady-state fan current draw — — SENSE: SENSE frequency pulses per fan —...

  • Page 100: Boxed Processor Fan Heatsink Airspace Keepout Requirements (Top View)

    Boxed Processor Specifications Figure 8-7. Boxed Processor Fan Heatsink Airspace Keepout Requirements (top view) Figure 8-8. Boxed Processor Fan Heatsink Airspace Keepout Requirements (side view) Datasheet, Volume 1...

  • Page 101: Variable Speed Fan

    Boxed Processor Specifications 8.4.2 Variable Speed Fan If the boxed processor fan heatsink 4-pin connector is connected to a 3-pin motherboard header, it will operate as follows: The boxed processor fan will operate at different speeds over a short range of internal chassis temperatures.
  • Page 102 As processor power has increased, the required thermal solutions have generated increasingly more noise. Intel has added an option to the boxed processor that allows system integrators to have a quieter system in the most common usage.

This manual is also suitable for:

Core i7-970Core i7-990xCore i7-980Core i7-980x

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