Table 2-67. M_Msr_Pmu_Cnt_Ctl{5-0} Register - Field Definitions; Table 2-68. M_Msr_Pmu_Cnt_{5-0} Register - Field Definitions - Intel BX80571E7500 - Core 2 Duo 2.93 GHz Processor Programming Manual

I ® X ® P 7500 S
NTEL EON ROCESSOR
Table 2-67. M_MSR_PMU_CNT_CTL{5-0} Register – Field Definitions
Field
ig
rsv
ig
rsv
set_flag_sel
rsv
inc_sel
rsv
flag_mode
wrap_mode
storage_mode
count_mode
pmi_en
en
The M-Box performance monitor data registers are 48b wide. A counter overflow occurs when a carry
out bit from bit 47 is detected. Software can force all uncore counting to freeze after N events by
preloading a monitor with a count value of (2
the U-Box. Upon receipt of the PMI, the U-Box will disable counting (
Counter Overflow"). During the interval of time between overflow and global disable, the counter value
will wrap and continue to collect events.
In this way, software can capture the precise number of events that occurred between the time uncore
counting was enabled and when it was disabled (or 'frozen') with minimal skew.
If accessible, software can continuously read the data registers without disabling event collection.
Table 2-68. M_MSR_PMU_CNT_{5-0} Register – Field Definitions
Field
event_count
The M-Box also includes a 16b timestamp unit that is incremented each M-Box clock tick. It is a free-
running counter unattached to the rest of the M-Box PMU, meaning it does not generate an event fed to
the other counters.
U P G
ERIES NCORE ROGRAMMING UIDE
HW
Bits Reset
Val
63 0 Read zero; writes ignored. (?)
62:61 0 Reserved; Must write to 0 else behavior is undefined.
60:25 0 Read zero; writes ignored. (?)
24:22 0 Reserved; Must write to 0 else behavior is undefined.
21:19 0 Selects the 'set' condition for enable flag. Secondary event select.
See
events elected by this field.
NOTE: Bit 7 (flag_mode) must be set to 1 to enable this field.
18:14 0 Reserved; Must write to 0 else behavior is undefined.
13:9 0 Selects increment signal for this counter. Primary event select.
See
events elected by this field.
8 0 Reserved; Must write to 0 else behavior is undefined.
7 0 Enable conditional counting using set_flag_sel
6 0 Counter wrap mode. If set to 0, this counter will stop counting on
detection of over/underflow. If set to 1, this counter will wrap and
continue counting on detection of over/underflow.
5:4 0 Storage mode. If set to 0, no count enable flag is required. If set to 1,
count enable flag must have a value of 1 for counting to occur.
3:2 0 00 - count will increase (up)
01 - count will decrease (dn)
10 - count can increase and decrease
1 0 Enable PMON interrupt on counter over/underflow.
0 0 Enable counting
- 1) - N and setting the control register to send a PMI to
48
HW
Bits Reset
Val
47:0 0 48-bit performance event counter
UNCORE PERFORMANCE MONITORING
Description
Table 2-84, "Performance Monitor Events for M-Box Events"
Table 2-84, "Performance Monitor Events for M-Box Events"
Section 2.1.1.1, "Freezing on
Description
for
for
2-101