Related Manuals for Intel BX80569Q9550 - Core 2 Quad 2.83 GHz Processor
Summary of Contents for Intel BX80569Q9550 - Core 2 Quad 2.83 GHz Processor
- Page 1 ® ® Intel Itanium Processor 9300 Series and 9500 Series Specification Update November 2012 Reference Number: 323169-010...
- Page 2 A “Mission Critical Application” is any application in which failure of the Intel Product could result, directly or indirectly, in personal injury or death. SHOULD YOU PURCHASE OR USE INTEL'S PRODUCTS FOR ANY SUCH MISSION CRITICAL APPLICATION, YOU...
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Page 3: Table Of Contents
Contents Revision History ......................4 Preface ...........................5 Identification Information ....................7 Summary Table of Changes .....................8 ® ® Intel Itanium Processor 9300 Series Errata .............. 13 ® ® Intel Itanium Processor 9500 Series Errata .............. 30 ® ® Intel Itanium Processor 9300 Series and 9500 Series... -
Page 4: Revision History
® ® Added Intel Itanium Processor 9300 Series Errata 116. 323169-009 September 2012 ® ® Modified summary table for Intel Itanium Processor 9300 Series Errata 58, 59. ® ® Added Intel Itanium Processor 9300 Series Errata 117. 323169-010 November 2012 ®... -
Page 5: Preface
Document # ® ® Intel Itanium Processor 9300 Series and 9500 Series Datasheet 322821-002 Intel Itanium Processor 9300 Series Reference Manual for Software Development and Optimization 323602 245317, 245318, ® ® Intel Itanium Architecture Software Developer’s Manual, Volumes 1 through 4 323207, 323208 ®... - Page 6 Specification changes, specification clarifications and documentation changes are removed from the specification update when the appropriate changes are made to the appropriate product specification or user documentation (datasheets, manuals, and so forth). ® ® Intel Itanium Processor 9300 Series and 9500 Series November 2012 Specifiication Update...
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Page 7: Identification Information
Identification Information ® ® Table 3. Intel Itanium Processor 9300 Series Stepping Summary Processor S-Spec Processor Stepping CPUID Cores Core Freq Number Number (MB) Revision LBMX 9350 0020020404 1.73 GHz with turbo up to 1.86 GHz LBMW 9340 0020020404 1.60 GHz with turbo up to 1.73 GHz... -
Page 8: Summary Table Of Changes
Summary Table of Changes The following tables indicate the errata, specification changes, and specification clarifications which apply to the processor. Intel may fix some of the errata in a future stepping of the component, and account for the other outstanding issues through documentation or specification changes as noted. -
Page 9: Intel Itanium Processor 9300 Series Errata
Northbound Intel SMI CRC Persistent Error Can No Fix Cause South Bound CRCs Resulting In Fast Reset Loop ® CRC Errors Occur on Intel QPI After Physical No Fix Layer Reset When Scrambling And Periodic Retraining Are Enabled No Fix... - Page 10 PAL_SHUTDOWN Has Incorrect Index PAL_ECC_ERROR_MASK Does Not Check Mask For Fixed Determining No Error ® Rbox Blocking And Intel QPI Min Credit Occurring No Fix At The Same Time With Some Traffic Patterns Can Cause Hang Persistent CRC Error During Aggressive Pin...
- Page 11 A Memory Update Operation May Not Complete Fixed Properly When An L2 Cache Line Encounters a Second Single Bit Data Error Intel Cache Safe Technology May Exceed 66 L2D Fixed Lines Disabled By One Intel Cache Safe Technology Event That Occurs In...
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Page 12: Intel Itanium Processor 9500 Series Errata
QPI State Machine Does Not Increment On Every Initialization Failure No Fix Instance ® ® No Fix Intel SMIPbox Does Not Drop Lanes Without Termination on Intel No Fix FPU Denormal SWA Priority Change PAL_PERF_MON_INFO Has Implementation Specific Requirements For cycles No Fix And retired ®... - Page 13 Implication: Deadlock conditions in some code sequences involving PAL-based IA-32 execution and PTC.G can occur if workaround is not applied. Workaround: Contact your Intel technical representative for details on workaround. Status: No Fix. ® Error During Intel QPI Link Initialization Can Cause Hang ®...
- Page 14 16-bit CRC is changed to 8-bit CRC, or 8-bit CRC is changed to 16-bit CRC. This can ® possibly triggering ERROR# 301, “Rbox Intel QuickPath Interconnect CRC Error” if enabled. Use the following flow when performing a link layer reset where the CRC mode is set or changed to 16-bit rolling CRC.
- Page 15 SMI. The processor is unable to signal an MCA in response to this Zbox error due to the pending reset. A cold reset is required to recover from this state. Implication: FPGA or other system logic should not directly reset the Intel 7500 Scalable Memory Buffer on a warm-state or warm-logic reset. Workaround: Firmware should provide some capabilities so that it can control the Scalable Memory Buffer reset on warm reset.
- Page 16 Frame Alert Logged After Warm-Logic Reset Problem: After a warm-logic reset where the Intel 7500 Scalable Memory Buffer is not reset, the Zbox will log a “Zbox Memory Alert Error” Error# 605. Error# 605 does not cause any response. Its only response is to set Z_CSR_ERR_LOG.status_frm_alert. In addition, Z_CSR_CHNL_ERR_LOG.sts_frm_alert_ch[1-0] will be set to '11 which notifies the...
- Page 17 The Error #617 is persistent enough to cause a fast reset due to the CRC threshold being hit. The Error #617 will occur on subsequent fast resets causing ® ® the Intel SMI link to loop on fast resets. This does not affect Intel QPI links. Implication: Error #617 is incorrectly logged. ®...
- Page 18 Error# 302. The condition self heals, but respective errors are ® logged. Error# 302 is recoverable and an MCA will be issued. On the Intel 7500 Chipset, a B1 Error will be logged (versus an Error#302 on the processor).
- Page 19 Disabled In Set Problem: When Intel Cache Safe Technology disables any of the 8 ways in a set, the ways which are not disabled are used for the fill. For the L2i one preferred way will always be selected for a set if all the enabled ways are valid. If any of the valid ways in an affected set are invalidated, there will be no preferred way and the replacement algorithm for L2i will fill as expected.
- Page 20 When the memory controller issues a write to the Intel 7500 Scalable Memory Buffer, the memory controller waits a round trip latency to confirm the southbound command arrived at the ®...
- Page 21 • If a Link error occurs on southbound write data, the Intel 7500 Scalable Memory Buffer will write data with BAD ECC to DRAM. The memory controller ECC would catch this, and should fix resulting in correctable error.
- Page 22 ® needs to take into account the impact of Intel QPI Periodic Retraining disabled. Contact your Intel Technical representative for questions on or analysis of your thermal ® and environmental testing around Intel QPI Periodic Retraining.
- Page 23 Neither thread on a core entering SAL_CHECK during a SYSINIT MCA ® Problem: When the SYSINT MCA PAL thread semaphore is owned and the Intel QPI viral bit is set, the semaphore is not released causing the SYSINIT MCA to be continuously signaled.
- Page 24 When testing INITs prior to initialization of the MINSTATE area, it will result in a hang or an illegal address access. Workaround: None at this time. Status: Fixed in PAL 4.29. ® ® Intel Itanium Processor 9300 Series and 9500 Series November 2012 Specifiication Update...
- Page 25 Any transaction type may be randomly assigned to any level of timeout. Similarly, the timeout hierarchy described in the QPI specification is not ® ® preserved on Intel Itanium Processor 9300 Series. Implication: Miscorrelation of timeout level to transaction type can lead to false timeout failures.
- Page 26 ® ® Intel QPI logic in the processor is in some internal states, some failed Intel QPI link layer inits would not be recorded in the counter. These missed counts can cause a delay in when the count limit would be reached.
- Page 27 6 hours on one core in any one level of cache. The burst may or may not reach the Intel Cache Safe Technology limit for that cache array. The burst behavior can appear for any length of time, disappear, and reoccur.
- Page 28 116. Intel Cache Safe Technology May Exceed 66 L2D Lines Disabled By Problem: There are some instances where PAL may disable 67 L2D lines by Intel Cache Safe Technology instead of the expected 66 limit. Implication: There are no execution side effects – besides the extra L2D line disabled.
- Page 29 PAL_MEMORY_BUFFER PAL will incorrectly handoff to SAL_CHECK with psp.hd bit set. Implication: The part is not “hardware damaged” as defined by Intel® Itanium® Architecture Software Developer’s Manual, but implication depends on the OS action/response to the “hardware damaged” set at SAL_CHECK.
- Page 30 Scalable Memory Buffer Must Not Be Reset Directly by FPGA or Other System Logic On Warm Reset Problem: On a warm-state or warm-logic reset an Intel Scalable Memory Buffer can be reset ® sooner than the processor. When this occurs the Zbox detects an error on Intel SMI.
- Page 31 Frame Alert Logged After Warm-Logic Reset Problem: After a warm-logic reset where the Intel Scalable Memory Buffer is not reset, the Zbox will log a “Zbox Memory Alert Error” Error# 605. Error# 605 does not cause any response. Its only response is to set Z_CSR_ERR_LOG.status_frm_alert. In addition, Z_CSR_CHNL_ERR_LOG.sts_frm_alert_ch[1-0] will be set to '11 which notifies the...
- Page 32 Corrupted ALERT Frame Not Detected By Zbox Problem: Any corrupted ALERT frame will not be detected by the processor. Since the Intel Scalable Memory Buffer issues a series of ALERT frames, in most cases missing an ALERT frame is not an issue. There is no CRC protection on ALERT frames, and the processor does not have a mechanism to detect corrupt Alert Frames.
- Page 33 • If a Link error occurs on southbound write data, the Intel Scalable Memory Buffer will write data with BAD ECC to DRAM. The memory controller ECC would catch this, and should fix resulting in correctable error.
- Page 34 “Limit Check?” for frcpa/frsqrta follow the “UnNormal Operand?”. “Limit Check?” will always fail if (Denormal Enabled and UnNormal Operand). ® Implication: There should not be any impact to this behavior. It a deviation from the Intel ® Itanium Architecture Software Developer’s Manual. Workaround: None required.
- Page 35 QPI Dynamic Link Width Reduction may result in quarter width mode when half ® width mode is expected. When this occurs the Intel QPI link width will not come up as specified by TDC. Cross talk may cause the processor receivers to detect data patterns on floating lanes and can result in this condition.
- Page 36 QPI Alternate clock before link training. Alternatively to maintain ® ® Intel QPI Alternate clock enabled, use 16-b rolling CRC and quarter-width Intel as the failover link width via PQ_CSR_PHWCI. This mitigates this issue which occurs in alternate clock mode. Status: No Fix.
- Page 37 This is due to poison being logged and not cleared in the floating point registers file following the error reset. Implication: Thread appears missing following an Error Reset. Workaround: None at this time. Intel can help diagnose if Minstate Memory is captured for any threads. Status: Fixed in PAL 4.13. §...
- Page 38 ® ® Intel Itanium Processor 9300 Series and 9500 Series November 2012 Specifiication Update...