W-Box Pmon State - Counter/Control Pairs; Table 2-96. W_Msr_Pmon_Global_Status Register Fields; Table 2-97. W_Msr_Pmon_Global_Ovf_Ctrl Register Fields - Intel BX80571E7500 - Core 2 Duo 2.93 GHz Processor Programming Manual

I ® X ® P 7500 S
NTEL EON ROCESSOR
Field
ov_fixed
ig
ov
Field
clr_ov_fixed
ig
clr_ov
2.8.3.2

W-Box PMON state - Counter/Control Pairs

The following table defines the layout of the W-Box performance monitor control registers. The main
task of these configuration registers is to select the event to be monitored by their respective data
counter. Setting the .ev_sel and .umask fields performs the event selection. The .en bit must be set to
1 to enable counting.
Additional control bits include:
- .pmi_enable governs what to do if an overflow is detected.
- .threshold - since C-Box counters can increment by a value greater than 1, a threshold can be applied.
If the .threshold is set to a non-zero value, that value is compared against the incoming count for that
event in each cycle. If the incoming count is >= the threshold value, then the event count captured in
the data register will be incremented by 1. (Not present in fixed counter)
- .invert - Changes the .threshold test condition to '<' (Not present in fixed counter)
- .edge_detect - Rather than accumulating the raw count each cycle (for events that can increment by
1 per cycle), the register can capture transitions from no event to an event incoming. (Not present in
fixed counter)
U P
ERIES NCORE ROGRAMMING

Table 2-96. W_MSR_PMON_GLOBAL_STATUS Register Fields

HW
Bits Reset
Val
31 0
30:4 0
3:0 0

Table 2-97. W_MSR_PMON_GLOBAL_OVF_CTRL Register Fields

HW
Bits Reset
Val
31 0
30:4 0
5:0 0
G
UIDE
Description
If an overflow is detected from the WBOX PMON fixed counter, this bit
will be set.
Read zero; writes ignored. (?)
If an overflow is detected from the corresponding WBOX PMON
register, it's overflow bit will be set.
Description
Writing '1' to bit in field causes corresponding bit in 'Overflow PerfMon
Counter' field in W_MSR_PMON_GLOBAL_STATUS register to be
cleared to 0.
Read zero; writes ignored. (?)
Writing '1' to bit in field causes corresponding bit in 'Overflow PerfMon
Counter' field in W_MSR_PMON_GLOBAL_STATUS register to be
cleared to 0.
UNCORE PERFORMANCE MONITORING
2-126