Table 2-13. C_Msr_Pmon_Evt_Sel{5-0} Register - Field Definitions; Table 2-14. C_Msr_Pmon_Ctr{5-0} Register - Field Definitions - Intel BX80571E7500 - Core 2 Duo 2.93 GHz Processor Programming Manual

I ® X ® P 7500 S
NTEL EON ROCESSOR
Table 2-13. C_MSR_PMON_EVT_SEL{5-0} Register – Field Definitions
Field
ig
rsv
ig
threshold
invert
en
ig
pmi_en
ig
edge_detect
ig
umask
ev_sel
The C-Box performance monitor data registers are 48b wide. A counter overflow occurs when a carry
out bit from bit 47 is detected. Software can force all uncore counting to freeze after N events by
preloading a monitor with a count value of 2
U-Box. Upon receipt of the PMI, the U-Box will disable counting (
Overflow"). During the interval of time between overflow and global disable, the counter value will wrap
and continue to collect events.
In this way, software can capture the precise number of events that occurred between the time uncore
counting was enabled and when it was disabled (or 'frozen') with minimal skew.
If accessible, software can continuously read the data registers without disabling event collection.
Table 2-14. C_MSR_PMON_CTR{5-0} Register – Field Definitions
Field
event_count
U P G
ERIES NCORE ROGRAMMING UIDE
HW
Bits Reset
Val
63 0 Read zero; writes ignored. (?)
62:61 0 Reserved; Must write to 0 else behavior is undefined.
60:50 0 Read zero; writes ignored. (?)
31:24 0 Threshold used in counter comparison.
23 0 When 0, the comparison that will be done is threshold <= event. When
set to 1, the comparison that is inverted (e.g. threshold < event)
22 0 Local Counter Enable. When set, the associated counter is locally
enabled.
NOTE: It must also be enabled in C_MSR_PMON_GLOBAL_CTL and the
U-Box to be fully enabled.
21 0 Read zero; writes ignored. (?)
20 0 When this bit is asserted and the corresponding counter overflows, a PMI
exception is sent to the U-Box.
19 0 Read zero; writes ignored. (?)
18 0 When asserted, the 0 to 1 transition edge of a 1 bit event input will cause
the corresponding counter to increment. When 0, the counter will
increment for however long the event is asserted.
NOTE: .edge_detect is in series following threshold and invert, so it can
be applied to multi-increment events that have been filtered by the
threshold field.
17:16 0 Read zero; writes ignored. (?)
15:8 0 Select subevents to be counted within the selected event.
7:0 0 Select event to be counted.
- N and setting the control register to send a PMI to the
48
HW
Bits Reset
Val
47:0 0 48-bit performance event counter
UNCORE PERFORMANCE MONITORING
Description
Section 2.1.1.1, "Freezing on Counter
Description
2-15