Table 2-44. R_Msr_Pmon_Ctl{15-0} Register - Field Definitions - Intel BX80571E7500 - Core 2 Duo 2.93 GHz Processor Programming Manual

I ® X ® P 7500 S
NTEL EON ROCESSOR
Table 2-44. R_MSR_PMON_CTL{15-0} Register – Field Definitions
Field
ig
rsv
ig
pmi_en
ev_sel
en
U P G
ERIES NCORE ROGRAMMING UIDE
HW
Bits Reset
Val
63 0 Read zero; writes ignored. (?)
62:61 0 Reserved; Must write to 0 else behavior is undefined.
60:7 0 Read zero; writes ignored. (?)
6 0 When this bit is asserted and the corresponding counter overflows, a PMI
exception is sent to the U-Box.
5:1 0 Event Select
For the R-Box this means choosing which sub register contains the actual
event select. Each control register can redirect the event select to one of
3 sets of registers: QLX, RIX or Mask/Match registers. It can further
select from one of two subselect fields (either in the same or different
registers).
And finally, each control can 'listen' to events occurring on one of 4 ports.
The first 8 control registers can refer to the first 4 ports and the last 8
control
So, for example:
RP_CR_R_CSR_PMON_CTL9 can refer to R_CSR_PORT{4-7}_IPERF{0-
1}
0 0 Enable counter
UNCORE PERFORMANCE MONITORING
Description
2-79