R-Box Pmu - Overflow, Freeze And Unfreeze; R-Box Performance Monitors; R-Box Performance Monitoring Msrs - Intel BX80571E7500 - Core 2 Duo 2.93 GHz Processor Programming Manual

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3) Pick a generic counter (control+data) that can monitor an event on that port. (e.g
R_MSR_PMON_CTL/CTR3)
4) Pick one of the two sub counters that allows a user to monitor the event (R_MSR_PORT1_IPERF1),
program it to monitor the chosen event (R_MSR_PORT1_IPERF1[31] = 0x1) and set the generic control
to point to it (R_MSR_PMON_CTL3.ev_sel == 0x7).
5) Enable the counter (e.g. R_MSR_PMON_CTL3.en == 0x1)
2.6.2.2

R-Box PMU - Overflow, Freeze and Unfreeze

If an overflow is detected from a R-Box performance counter, the overflow bit is set at the box level
(R_MSR_PMON_GLOBAL_STATUS_15_8.ov for the R side and R_MSR_PMON_GLOBAL_STATUS_7_0.ov
for the L), and forwarded up the chain towards the U-Box. If counter overflows in the left R-Box, a
notification is sent and stored in S-Box0 (S_MSR_PMON_SUMMARY.ov_c_l) which, in turn, sends the
overflow notification up to the U-Box (U_MSR_PMON_GLOBAL_STATUS.ov_s0). Refer to
"S_MSR_PMON_SUMMARY Register Fields"
in the attached S-Box.
HW can be also configured (by setting the corresponding .pmi_en to 1) to send a PMI to the U-Box
when an overflow is detected. The U-Box may be configured to freeze all uncore counting and/or send a
PMI to selected cores when it receives this signal.
Once a freeze has occurred, in order to see a new freeze, the overflow field responsible for the freeze,
must be cleared by setting the corresponding bit in R_MSR_PMON_GLOBAL_OVF_CTL.clr_ov. Assuming
all the counters have been locally enabled (.en bit in data registers meant to monitor events) and the
overflow bit(s) has been cleared, the R-Box is prepared for a new sample interval. Once the global
controls have been re-enabled
Counters"), counting will resume.
2.6.3

R-BOX Performance Monitors

R_MSR_PORT7_XBR_SET2_MASK
R_MSR_PORT7_XBR_SET2_MATCH
R_MSR_PORT7_XBR_SET2_MM_CFG
R_MSR_PORT7_XBR_SET1_MASK
R_MSR_PORT7_XBR_SET1_MATCH
R_MSR_PORT7_XBR_SET1_MM_CFG
R_MSR_PORT6_XBR_SET2_MASK
R_MSR_PORT6_XBR_SET2_MATCH
R_MSR_PORT6_XBR_SET2_MM_CFG
R_MSR_PORT6_XBR_SET1_MASK
R_MSR_PORT6_XBR_SET1_MATCH
R_MSR_PORT6_XBR_SET1_MM_CFG
R_MSR_PORT5_XBR_SET2_MASK
R_MSR_PORT5_XBR_SET2_MATCH
R_MSR_PORT5_XBR_SET2_MM_CFG
U P G
ERIES NCORE ROGRAMMING UIDE
to determine how each R-Box's overflow bit is accumulated
(Section 2.1.4, "Enabling a New Sample Interval from Frozen
Table 2-39. R-Box Performance Monitoring MSRs
MSR Name
UNCORE PERFORMANCE MONITORING
MSR
Size
Access Addres
(bits)
s
RW_NA 0x0E9E 64 R-Box Port 7 Mask 2
RW_NA 0x0E9D 64 R-Box Port 7 Match 2
RW_NA 0x0E9C 64 R-Box Port 7 Mask/Match Config 2
RW_NA 0x0E8E 64 R-Box Port 7 Mask 1
RW_NA 0x0E8D 64 R-Box Port 7 Match 1
RW_NA 0x0E8C 64 R-Box Port 7 Mask/Match Config 1
RW_NA 0x0E9A 64 R-Box Port 6 Mask 2
RW_NA 0x0E99 64 R-Box Port 6 Match 2
RW_NA 0x0E98 64 R-Box Port 6 Mask/Match Config 2
RW_NA 0x0E8A 64 R-Box Port 6 Mask 1
RW_NA 0x0E89 64 R-Box Port 6 Match 1
RW_NA 0x0E88 64 R-Box Port 6 Mask/Match Config 1
RW_NA 0x0E96 64 R-Box Port 5 Mask 2
RW_NA 0x0E95 64 R-Box Port 5 Match 2
RW_NA 0x0E94 64 R-Box Port 5 Mask/Match Config 2
Table 2-26,
Description
2-74