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ERRATA
C1.
FP Data Operand Pointer May Be Incorrectly Calculated After
FP Access Which Wraps 64-Kbyte Boundary in 16-Bit Code
The FP Data Operand Pointer is the effective address of the operand associated with the last
Problem:
noncontrol floating-point instruction executed by the machine. If an 80-bit floating-point access (load or store)
occurs in a 16-bit mode other than protected mode (in which case the access will produce a segment limit
violation), the memory access wraps a 64-Kbyte boundary, and the floating-point environment is subsequently
saved, the value contained in the FP Data Operand Pointer may be incorrect.
A 32-bit operating system running 16-bit floating-point code may encounter this erratum, under
Implication:
the following conditions:
•
The operating system is using a segment greater than 64 Kbytes in size.
•
An application is running in a 16-bit mode other than protected mode.
•
An 80-bit floating-point load or store which wraps the 64-Kbyte boundary is executed.
•
The operating system performs a floating-point environment store (FSAVE/FNSAVE/FSTENV/FNSTENV)
after the above memory access.
•
The operating system uses the value contained in the FP Data Operand Pointer.
Wrapping an 80-bit floating-point load around a segment boundary in this way is not a normal programming
practice. Intel has not currently identified any software which exhibits this behavior.
If the FP Data Operand Pointer is used in an OS which may run 16-bit floating-point code,
Workaround:
care must be taken to ensure that no 80-bit floating-point accesses are wrapped around a 64-Kbyte boundary.
For the steppings affected see the Summary of Changes at the beginning of this section.
Status:
C2.
Differences Exist in Debug Exception Reporting
There exist some differences in the reporting of code and data breakpoint matches between that
Problem:
specified by previous Celeron processor specifications and the behavior of Celeron processor, as described
below:
Case 1: The first case is for a breakpoint set on a MOVSS or POPSS instruction, when the instruction
following it causes a debug register protection fault (DR7.gd is already set, enabling the fault). The Celeron
processor reports delayed data breakpoint matches from the MOVSS or POPSS instructions by setting the
matching DR6.bi bits, along with the debug register protection fault (DR6.bd). If additional breakpoint faults
are matched during the call of the debug fault handler, the Celeron processor sets the breakpoint match bits
(DR6.bi) to reflect the breakpoints matched by both the MOVSS or POPSS breakpoint and the debug fault
handler call. The Celeron processor only sets DR6.bd in either situation, and does not set any of the DR6.bi
bits.
Case 2: In the second breakpoint reporting failure case, if a MOVSS or POPSS instruction with a data
breakpoint is followed by a store to memory which:
a)
crosses a 4-Kbyte page boundary,
OR
®
INTEL
CELERON® PROCESSOR SPECIFICATION UPDATE
25
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