Intel SL3VS - Celeron 633 MHz Processor Specification page 58

®
INTEL CELERON® PROCESSOR SPECIFICATION UPDATE
C51. Floating-Point Exception Condition May be Deferred
A floating-point instruction that causes a pending floating-point exception (ES=1) is normally
Problem:
signaled by the processor on the next waiting FP/MMX™ technology instruction. In the following set of
circumstances, the exception may be delayed or the FSW register may contain a wrong value:
1. The excepting floating-point instruction is followed by an instruction that accesses
memory across a page (4 Kbyte) boundary or its access results in the update of a page
table dirty/access bit.
2. The memory accessing instruction is immediately followed by a waiting floating-point or
MMX technology instruction.
3. The waiting floating-point or MMX technology instruction retires during a one-cycle
window that coincides with a sequence of internal events related to instruction cache
line eviction.
The floating-point exception will not be signaled until the next waiting floating-point/MMX
Implication:
technology instruction. Alternatively it may be signaled with the wrong TOS and condition code values. This
erratum has not been observed in any commercial software applications.
None identified
Workaround:
For the stepping affected see the Summary of Changes at the beginning of this section.
Status:
C52. Cache Line Reads May Result in Eviction of Invalid Data
A small window of time exists in which internal timing conditions in the processor cache logic may
Problem:
result in the eviction of an L2 cache line marked in the invalid state.
There are three possible implications of this erratum:
Implication:
1. The processor may provide incorrect L2 cache line data by evicting an invalid line.
2. A BNR# (Block Next Request) stall may occur on the system bus.
3. Should a snoop request occur to the same cache line in a small window of time, the
processor may incorrectly assert HITM#. It is then possible for an infinite snoop stall to
occur should another processor respond (correctly) to the snoop request with HIT#. In
order for this infinite snoop stall to occur, at least three agents must be present, and
the probability of occurrence increases with the number of processors.
Should 2 or 3 occur, the processor will eventually assert BINIT# (if enabled) with an MCA error code
indicating a ROB time-out. At this point, the system requires a hard reset.
It is possible for BIOS code to contain a workaround for this erratum.
Workaround:
For the steppings affected, see the Summary of Changes at the beginning of this section.
Status:
50