Intel SL3VS - Celeron 633 MHz Processor Specification page 35

C4. FP Inexact-Result Exception Flag May Not Be Set
When the result of a floating-point operation is not exactly representable in the destination format
Problem:
(1/3 in binary form, for example), an inexact-result (precision) exception occurs. When this occurs, the PE bit
(bit 5 of the FPU status word) is normally set by the processor. Under certain rare conditions, this bit may not
be set when this rounding occurs. However, other actions taken by the processor (invoking the software
exception handler if the exception is unmasked) are not affected. This erratum can only occur if the floating-
point operation which causes the precision exception is immediately followed by one of the following
instructions:
•
FST m32real
•
FST m64real
•
FSTP m32real
•
FSTP m64real
•
FSTP m80real
•
FIST m16int
•
FIST m32int
•
FISTP m16int
•
FISTP m32int
•
FISTP m64int
Note that even if this combination of instructions is encountered, there is also a dependency on the internal
pipelining and execution state of both instructions in the processor.
Inexact-result exceptions are commonly masked or ignored by applications, as it happens
Implication:
frequently, and produces a rounded result acceptable to most applications. The PE bit of the FPU status word
may not always be set upon receiving an inexact-result exception. Thus, if these exceptions are unmasked, a
floating-point error exception handler may not recognize that a precision exception occurred. Note that this is
a "sticky" bit, i.e., once set by an inexact-result condition, it remains set until cleared by software.
This condition can be avoided by inserting two NOP instructions between the two floating-
Workaround:
point instructions.
For the steppings affected see the Summary of Changes at the beginning of this section.
Status:
C5. BTM for SMI Will Contain Incorrect FROM EIP
A system management interrupt (SMI) will produce a Branch Trace Message (BTM), if BTMs are
Problem:
enabled. However, the FROM EIP field of the BTM (used to determine the address of the instruction which
was being executed when the SMI was serviced) will not have been updated for the SMI, so the field will
report the same FROM EIP as the previous BTM.
A BTM which is issued for an SMI will not contain the correct FROM EIP, limiting the
Implication:
usefulness of BTMs for debugging software in conjunction with System Management Mode (SMM).
None identified
Workaround:
For the steppings affected see the Summary of Changes at the beginning of this section.
Status:
®
INTEL CELERON® PROCESSOR SPECIFICATION UPDATE
27