Intel SL3VS - Celeron 633 MHz Processor Specification page 37

C9. LBER May Be Corrupted After Some Events
The last branch record (LBR) and the last branch before exception record (LBER) can be used to
Problem:
determine the source and destination information for previous branches or exceptions. The LBR contains the
source and destination addresses for the last branch or exception, and the LBER contains similar information
for the last branch taken before the last exception. This information is typically used to determine the location
of a branch which leads to execution of code which causes an exception. However, after a catastrophic bus
condition which results in an assertion of BINIT# and the re-initialization of the buses, the value in the LBER
may be corrupted. Also, after either a CALL which results in a fault or a software interrupt, the LBER and LBR
will be updated to the same value, when the LBER should not have been updated.
The LBER and LBR registers are used only for debugging purposes. When this erratum
Implication:
occurs, the LBER will not contain reliable address information. The value of LBER should be used with caution
when debugging branching code; if the values in the LBR and LBER are the same, then the LBER value is
incorrect. Also, the value in the LBER should not be relied upon after a BINIT# event.
None identified
Workaround:
For the steppings affected see the Summary of Changes at the beginning of this section.
Status:
C10. BTMs May Be Corrupted During Simultaneous L1 Cache Line
Replacement
When Branch Trace Messages (BTMs) are enabled and such a message is generated, the BTM
Problem:
may be corrupted when issued to the bus by the L1 cache if a new line of data is brought into the L1 data
cache simultaneously. Though the new line being stored in the L1 cache is stored correctly, and no corruption
occurs in the data, the information in the BTM may be incorrect due to the internal collision of the data line and
the BTM.
Although BTMs may not be entirely reliable due to this erratum, the conditions necessary for
Implication:
this boundary condition to occur have only been exhibited during focused simulation testing. Intel has currently
not observed this erratum in a system level validation environment.
None identified
Workaround:
For the steppings affected see the Summary of Changes at the beginning of this section.
Status:
®
INTEL CELERON® PROCESSOR SPECIFICATION UPDATE
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