Documentation Changes - Intel SL3VS - Celeron 633 MHz Processor Specification

DOCUMENTATION CHANGES

The Documentation Changes listed in this section apply to the following documents:
•
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Pentium II Processor Developer's Manual
•
P6 Family of Processors Hardware Developer's Manual
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Intel Celeron Processor Datasheet
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Intel Architecture Software Developer's Manual, Volumes 1, 2, and 3
All Documentation Changes will be incorporated into a future version of the appropriate Celeron processor
documentation.
C1. SSE and SSE2 Instructions Opcodes
The note at the end of section 2.2 in the Intel Architecture Software Developer's Manual , Vol 2 : Instruction Set
Reference states:
NOTE:
Some of the SSE and SSE2 instructions have three-byte opcodes. For these three-byte opcodes,
the third opcode byte may be F2H, F3H, or 66H. For example, the SSE2 instruction CVTDQ2PD
has the three-byte opcode F3 OF E6. The third opcode byte of these three-byte opcodes should not
be thought of as a prefix, even though it has the same encoding as the operand size prefix (66H) or
one of the repeat prefixes (F2H and F3H). As described above, using the operand size and repeat
prefixes with SSE and SSE2 instructions is reserved.
It should state:
NOTE:
Some of the SSE and SSE2 instructions have three-byte opcodes. For these three-byte opcodes,
the third opcode byte may be F2H, F3H, or 66H. For example, the SSE2 instruction CVTDQ2PD
has the three-byte opcode F3 OF E6. The third opcode byte of these three-byte opcodes should not
be thought of as a prefix, even though it has the same encoding as the operand size prefix (66H) or
one of the repeat prefixes (F2H and F3H). As described above, using the operand size and repeat
prefixes with SSE and SSE2 instructions is reserved. It should also be noted that execution of SSE2
instructions on an Intel processor that does not support SSE2 (CPUID Feature flag register EDX bit
26 is clear) will result in unpredictable code execution.
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INTEL CELERON® PROCESSOR SPECIFICATION UPDATE
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