Intel SL3VS - Celeron 633 MHz Processor Specification page 63

C61. Memory Ordering Based Synchronization May Cause a
Livelock Condition in MP Systems
In an MP environment, the following sequence of code (or similar code) in two processors (P0 and
Problem:
P1) may cause them to each enter an infinite loop (livelock condition):
P0
MOV [xyz], EAX
.
.
.
MOV [abc], val1
wait0: MOV EBX, [abc] (7)
CMP EBX, val2
JNE wait0
The EAX and EBX can be any general-purpose register. Addresses [abc] and
[xyz] can be any location in memory and must be in the same bank of the L1
cache. Variables "val1" and "val2" can be any integer.
The algorithm above involves processors P0 and P1, each of which use loops to keep them synchronized with
each other. P1 is looping until instruction (6) in P0 is globally observed. Likewise, P0 will loop until instruction
(5) in P1 is globally observed.
The P6 architecture allows for instructions (1) and (7) in P0 to be dispatched to the L1 cache simultaneously.
If the two instructions are accessing the same memory bank in the L1 cache, the load (7) will be given higher
priority and will complete, blocking instruction (1).
Instructions (8) and (9) may then execute and retire, placing the instruction pointer back to instruction (7). This
is due to the condition at the end of the "wait0" loop being false. The livelock scenario can occur if the timing
of the wait0 loop execution is such that instruction (7) in P0 is ready for completion every time that instruction
(1) tries to complete. Instruction (7) will again have higher priority, preventing the data ([xyz]) in instruction (1)
from being written to the L1 cache. This causes instruction (6) in P0 to not complete and the sequence "wait0"
to loop infinitely in P0.
A livelock condition also occurs in P1 because instruction (6) in P0 does not complete (blocked by instruction
(1) not completing). The problem with this scenario is that P0 should eventually allow for instruction (1) to write
its data to the L1 cache. If this occurs, the data in instruction (6) will be written to memory, allowing the
conditions in both loops to be true.
Both processors will be stuck in an infinite loop, leading to a hang condition. Note that if P0
Implication:
receives any interrupt, the loop timing will be disrupted such that the livelock will be broken. The system timer,
a keystroke, or mouse movement can provide an interrupt that will break the livelock.
Use a LOCK instruction to force P0 to execute instruction (6) before instruction (7).
Workaround:
For the steppings affected, see the Summary of Changes at the beginning of this section.
Status:
®
INTEL CELERON® PROCESSOR SPECIFICATION UPDATE
P1
(1) wait1: MOV EBX, [abc]
CMP EBX, val1
JNE wait1
(6) MOV [abc], val2
(8)
(9)
NOTE
(2)
(3)
(4)
(5)
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