Intel SL3VS - Celeron 633 MHz Processor Specification page 46

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INTEL CELERON® PROCESSOR SPECIFICATION UPDATE
C25. Read Portion of RMW Instruction May Execute Twice
When the Celeron processor executes a read-modify-write (RMW) arithmetic instruction, with
Problem:
memory as the destination, it is possible for a page fault to occur during the execution of the store on the
memory operand after the read operation has completed but before the write operation completes.
If the memory targeted for the instruction is UC (uncached), memory will observe the occurrence of the initial
load before the page fault handler and again if the instruction is restarted.
This erratum has no effect if the memory targeted for the RMW instruction has no side-effects.
Implication:
If, however, the load targets a memory region that has side-effects, multiple occurrences of the initial load may
lead to unpredictable system behavior.
Hardware and software developers who write device drivers for custom hardware that may
Workaround:
have a side-effect style of design should use simple loads and simple stores to transfer data to and from the
device. Then the memory location will simply be read twice with no additional implications.
For the steppings affected see the Summary of Changes at the beginning of this section.
Status:
C26. Test Pin Must Be High During Power Up
The Celeron processor uses the PWRGOOD signal to ensure that no voltage sequencing issues
Problem:
arise; no pin assertions should cause the processor to change its behavior until this signal is asserted, when
all power supplies and clocks to the processor are valid and stable. However, if the TESTHI signal is at a low
voltage level when the core power supply comes up, it will cause the processor to enter an invalid test state.
If this erratum occurs, the system may boot normally however, L2 cache may not be initialized.
Implication:
Ensure that the 2.5 V (V
Workaround:
plane. If 2.5 V ramps after core, pull up TESTHI to 2.5 V (V
up will keep the signal from being asserted during power up. For new motherboard designs, it is
recommended that TESTHI be pulled up to 2.0 V (V
For the steppings affected see the Summary of Changes at the beginning of this section.
Status:
C27. Intervening Writeback May Occur During Locked Transaction
During a transaction which has the LOCK# signal asserted (i.e., a locked transaction), there is a
Problem:
potential for an explicit writeback caused by a previous transaction to complete while the bus is locked. The
explicit writeback will only be issued by the processor which has locked the bus, and the lock signal will not be
deasserted until the locked transaction completes, but the atomicity of a lock may be compromised by this
erratum. Note that the explicit writeback is an expected cycle, and no memory ordering violations will occur.
This erratum is, however, a violation of the bus lock protocol.
A chipset or third-party agent (TPA) which tracks bus transactions in such a way that locked
Implication:
transactions may only consist of a read-write or read-read-write-write locked sequence, with no transactions
intervening, may lose synchronization of state due to the intervening explicit writeback. Systems using
chipsets or TPAs which can accept the intervening transaction will not be affected.
The bus tracking logic of all devices on the system bus should allow for the occurrence of an
Workaround:
intervening transaction during a locked transaction.
38
) power supply ramps at or before the 2.0 V (V
CC 2.5
) with a 100K Ohm resistor. The internal pull-
CC 2.5
) using a 1K-10K Ohm resistor.
CC CORE
) power
CC CORE