Intel SL3VS - Celeron 633 MHz Processor Specification page 69

C73.
Memory Aliasing with Inconsistent A and D bits May Cause
Processor Deadlock
In the event that software implements memory aliasing by having two Page Directory
Problem:
Entries(PDEs) point to a common Page Table Entry(PTE) and the Accessed and Dirty bits for the two PDEs
are allowed to become inconsistent, the processor may become deadlocked.
This erratum has not been observed with commercially available software.
Implication:
Software that needs to implement memory aliasing in this way should manage the
Workaround:
consistency of the accessed and dirty bits.
For the steppings affected see the Summary of Changes at the beginning of this section.
Status:
C74.
Processor may Report Invalid TSS Fault Instead of Double
Fault During Mode C Paging
When an operating system executes a task switch via a Task State Segment (TSS) the CR3
Problem:
register is always updated from the new task TSS. In the mode C paging, once the CR3 is changed the
processor will attempt to load the PDPTRs. If the CR3 from the target task TSS or task switch handler TSS is
not valid then the new PDPTR will not be loaded. This will lead to the reporting of invalid TSS fault instead of
the expected Double fault.
Operating systems that access an invalid TSS may get invalid TSS fault instead of a Double
Implication:
fault.
Software needs to ensure any accessed TSS is valid.
Workaround:
Status: For the steppings affected see the Summary of Changes at the beginning of this section.
C75.
APIC Failure at CPU Core/System Bus Frequency of 766/66
MHz
Operation of the Advanced Programmable Interrupt Controller (APIC) with the Celeron processor
Problem:
is problematic at the CPU core/system bus frequency of 766/66 MHz. With the I/O APIC enabled in BIOS, the
Celeron processor may read an incorrect value from an APIC register. The Celeron processor may also
randomly corrupt the vector field of an otherwise valid APIC message. The invalid vector may cause
unexpected system behavior.
If this erratum occurs, the processor may hang or cause unexpected system behavior. The
Implication:
Celeron processor is commonly deployed on platforms with the I/O APIC option disabled. These systems are
unaffected by this erratum.
The system BIOS can disable use of the I/O APIC at the affected frequency.
Workaround:
Status: For the steppings affected see the Summary of Changes at the beginning of this section.
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INTEL CELERON® PROCESSOR SPECIFICATION UPDATE
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