Intel SL3VS - Celeron 633 MHz Processor Specification page 62

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INTEL CELERON® PROCESSOR SPECIFICATION UPDATE
C59. Potential Loss of Data Coherency During MP Data
Ownership Transfer
In MP systems, processors may be sharing data in different cache lines, referenced as line A and
Problem:
line B in the discussion below. When this erratum occurs (with the following example given for a 2-way MP
system with processors noted as 'P0' and 'P1'), P0 contains a shared copy of line B in its L1. P1 has a shared
copy of Line A. Each processor must manage the necessary invalidation and snoop cycles before that
processor can modify and source the results of any internal writes to the other processor.
There exists a narrow timing window when, if P1 requests a copy of line B it may be supplied by P0 in an
Exclusive state which allows P1 to modify the contents of the line with no further external invalidation cycles.
In this narrow window P0 may also retire instructions that use the original data present before P1 performed
the modification.
Multiprocessor or threaded application synchronization, required for low level data sharing, that
Implication:
is implemented via operating system provided synchronization constructs are not affected by this erratum.
Applications that rely upon the usage of locked semaphores rather than memory ordering are also unaffected.
This erratum does not affect uniprocessor systems. The existence of this erratum was discovered during
ongoing design reviews but it has not as yet been reproduced in a lab environment. Intel has not identified, to
date, any commercially available application or operating system software which is affected by this erratum. If
the erratum does occur one processor may execute software with the stale data that was present from the
previous shared state rather than the data written more recently by another processor.
Deterministic barriers beyond which program variables will not be modified can be achieved
Workaround:
via the usage of locked semaphore operations. These should effectively prevent the occurrence of this
erratum.
For the steppings affected, see the Summary of Changes at the beginning of this section.
Status:
C60. Misaligned Locked Access to APIC Space Results In a Hang
When the processor's APIC space is accessed with a misaligned locked access a machine check
Problem:
exception is expected. However, the processor's machine check architecture is unable to handle the
misaligned locked access.
If this erratum occurs the processor will hang. Typical usage models for the APIC address
Implication:
space do not use locked accesses. This erratum will not affect systems using such a model.
Ensure that all accesses to APIC space are aligned.
Workaround:
For the steppings affected, see the Summary of Changes at the beginning of this section.
Status:
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