Intel SL3VS - Celeron 633 MHz Processor Specification page 68

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INTEL CELERON® PROCESSOR SPECIFICATION UPDATE
C70.
Selector for the LTR/LLDT Register May Get Corrupted
The internal selector portion of the respective register (TR, LDTR) may get corrupted if, during a
Problem:
small window of LTR or LLDT system instruction execution, the following sequence of events occur:
1. Speculative write to a segment register that might follow the LTR or LLDT instruction
2. The read segment descriptor of LTR/LLDT operation spans a page (4 Kbytes) boundary; or causes
a page fault
Incorrect selector for LTR, LLDT instruction could be used after a task switch.
Implication:
Software can insert a serializing instruction between the LTR or LLDT instruction and the
Workaround:
segment register write.
For the steppings affected see the Summary of Changes at the beginning of this section.
Status:
C71.
INIT Does Not Clear Global Entries in the TLB
INIT may not flush a TLB entry when:
Problem:
1. The processor is in protected mode with paging enabled and the page global enable flag is set
(PGE bit of CR4 register)
2. G bit for the page table entry is set
3. TLB entry is present in TLB when INIT occurs
Software may encounter unexpected page fault or incorrect address translation due to a TLB
Implication:
entry erroneously left in TLB after INIT.
Write to CR3, CR4 or CR0 registers before writing to memory early in BIOS code to clear all
Workaround:
the global entries from TLB.
For the steppings affected see the Summary of Changes at the beginning of this section
Status:
C72.
VM Bit Will be Cleared on a Double Fault Handler
Following a task switch to a Double Fault Handler that was initiated while the processor was in
Problem:
virtual-8086 (VM86) mode, the VM bit will be incorrectly cleared in EFLAGS.
When the OS recovers from the double fault handler, the processor will no longer be in VM86
Implication:
mode.
None identified
Workaround:
For the steppings affected see the Summary of Changes at the beginning of this section.
Status:
60