Intel SL3VS - Celeron 633 MHz Processor Specification page 25

NO.
650h 651h 660h
A0 A1 A0
C68
C69
C70 X X X
C71 X X X
C72 X X X
C73 X X X
C74 X X X
C75
C76 X X X
C77 X X X
C78 X X X
C79 X X X
C80
C81
®
INTEL CELERON® PROCESSOR SPECIFICATION UPDATE
Summary of Errata
CPUID/Stepping
665h 683h 686h 68Ah
B0 B0 C0 D0
X
X
X X
X X X X
X X X X
X X X X
X X X X
X X
X X X X
X X X X
X X X X
X X X X
X
Plans
6B1h 6B4h
A1 B1
NoFix Snoop probe during FLUSH#
could cause L2 to be left in
shared state
Fixed Livelock May Occur Due to
IFU Line Eviction
Fixed Selector for the LTR/LLDT
register may get corrupted
X X NoFix
INIT does not clear global
entries in the TLB
X X NoFix
VM bit will be cleared on a
double fault handler
Memory aliasing with
X X NoFix
inconsistent A and D bits
may cause processor
deadlock
X X NoFix Processor may report invalid
TSS fault instead of Double
fault during mode C paging
Fixed APIC failure at CPU
core/system bus frequency
of 766/66 MHz
X X NoFix Machine check exception
may occur when interleaving
code between different
memory types
X X NoFix Wrong ESP Register Values
During a Fault in VM86 Mode
X X NoFix APIC ICR Write May Cause
Interrupt Not to be Sent
When ICR Delivery Bit
Pending
X Fixed The instruction fetch unit
(IFU) may fetch
instructions based upon stale
CR3 data after a write to
CR3 Register
NoFix Processor Might not Exit
Sleep State Properly Upon
De-assertion of CPUSLP#
Signal
X X NoFix During Boundary Scan, BCLK
not Sampled High When
ERRATA
17