Intel SL3VS - Celeron 633 MHz Processor Specification page 56

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INTEL CELERON® PROCESSOR SPECIFICATION UPDATE
C47. Task Switch May Cause Wrong PTE and PDE Access Bit to
be Set
If an operating system executes a task switch via a Task State Segment (TSS), and the TSS is
Problem:
wholly or partially located within a clean page (A and D bits clear) and the GDT entry for the new TSS is either
misaligned across a cache line boundary or is in a clean page, the accessed and dirty bits for an incorrect
page table/directory entry may be set.
An operating system that uses hardware task switching (or hardware task management) may
Implication:
encounter this erratum. The effect of the erratum depends on the alignment of the TSS and ranges from no
anomalous behavior to unexpected errors.
The operating system could align all TSSs to be within page boundaries and set the A and D
Workaround:
bits for those pages to avoid this erratum. The operating system may alternately use software task
management.
For the steppings affected see the Summary of Changes at the beginning of this section.
Status:
C48. Cross Modifying Code Operations on a Jump Instruction
May Cause a General Protection Fault
The act of one processor writing data into the currently executing code segment of a second
Problem:
processor with the intent of having the second processor execute that data as code is called Cross-Modifying
Code (XMC). Software using XMC to modify the offset of an execution transfer instruction (i.e., Jump, Call
etc.), without a synchronizing instruction may cause a General Protection Fault (GPF) when the offset splits a
cache line boundary.
Any application creating a (GPF) would be terminated by the operating system.
Implication:
Programmers should use the cross modifying code synchronization algorithm as detailed in
Workaround:
Volume 3 of the Intel Architecture Software Developer's Manual , section 7.1.3, in order to avoid this erratum.
For the steppings affected see the Summary of Changes at the beginning of this section.
Status:
48