Intel SL3VS - Celeron 633 MHz Processor Specification page 77

Implication: This is a rare condition that may result in a system hang. Intel has not observed
this erratum with any commercially available software, or system.
Workaround: Avoid code that wraps around segment limit.
Status: For the steppings affected, see the Summary Tables of Changes.
C90. FST Instruction with Numeric and Null Segment Exceptions
May take Numeric Exception with Incorrect FPU Operand
Pointer
Problem: If execution of an FST (Store Floating Point Value) instruction would generate
both numeric and null segment exceptions, the numeric exception may be taken
first and with the Null x87 FPU Instruction Operand (Data) Pointer.
Implication: Due to this erratum, on an FST instruction the processor reports a numeric
exception instead of reporting an exception because of a Null segment. If the
numeric exception handler tries to access the FST data it will get a #GP fault.
Intel had not observed this erratum with any commercially available software, or
system.
Workaround: The numeric exception handler should check the segment and if it is Null avoid
further access to the data that caused the fault.
Status:
For the steppings affected, see the Summary Tables of Changes
C91. Code Segment (CS) Is Wrong on SMM Handler when SMBASE
Is Not Aligned
Problem:
With SMBASE being relocated to a non-aligned address, during SMM entry the
CS can be improperly updated which can lead to an incorrect SMM handler.
Implication: This is a rare condition that may result in a system hang. Intel has not observed
this erratum with any commercially available software, or system.
Workaround: Align SMBASE to 32K byte.
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INTEL CELERON® PROCESSOR SPECIFICATION UPDATE
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