Intel SL3VS - Celeron 633 MHz Processor Specification page 54

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INTEL CELERON® PROCESSOR SPECIFICATION UPDATE
C43. Internal Cache Protocol Violation May Cause System Hang
A Celeron processor-based system may hang due to an internal cache protocol violation. During
Problem:
multiple transactions targeted at the same cacheline, there exists a small window of time such that the
processor's internal timings align to create a livelock situation. The scenario, which results in the erratum, is
summarized below:
Scenario:
1. A snoopable transaction is issued to address A. This snoopable transaction can be issued by the
processor or the chipset.
2. The snoopable transaction hits a modified line in the processor's L1 data cache.
3. The processor issues two code fetches from the L2 cache before the snoopable transaction reaches the
top of the In-Order Queue and before the snoopable transaction's modified L1 cache line containing
address A is brought out on the system bus.
At the same time, a locked access to the L1 cache occurs.
A Celeron processor may cause a system to hang if the above listed sequence of events occur.
Implication:
The probability of encountering this erratum increases with I/O queue depth greater than four.
It is possible for the BIOS code to contain a workaround for this erratum.
Workaround:
For the steppings affected see the Summary of Changes at the beginning of this section.
Status:
C44. GP# Fault on WRMSR to ROB_CR_BKUPTMPDR6
Writing a '1' to unimplemented bit(s) in the ROB_CR_BKUPTMPDR6 MSR (offset 1E0h) will result
Problem:
in a general protection fault (GP#).
The normal process used to write an MSR is to read the MSR using RDMSR, modify the bit(s)
Implication:
of interest, and then to write the MSR using WRMSR. Because of this erratum, this process may result in a
GP# fault when used to modify the ROB_CR_BKUPTMPDR6 MSR.
When writing to ROB_CR_BKUPTMPDR6 all unimplemented bits must be '0.' Implemented
Workaround:
bits may be set as '0' or '1' as desired.
For the steppings affected see the Summary of Changes at the beginning of this section.
Status:
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