Intel SL3VS - Celeron 633 MHz Processor Specification page 27

NO.
650h 651h 660h
A0 A1 A0
C93 X X X
C93 X X X
C94 X X X
C95 X X X
C96 X X X
C97 X X X
C98 X X X
C99 X X X
C100 X X X
®
INTEL CELERON® PROCESSOR SPECIFICATION UPDATE
Summary of Errata
CPUID/Stepping
665h 683h 686h 68Ah
B0 B0 C0 D0
X X X X
X X X X
X X X X
X X X X
X X X X
X X X X
X X X
X
X X X
X
X X X
X
Plans
6B1h 6B4h
A1 B1
(Uncacheable) May
Consolidate to UC
Under Certain Conditions LTR
X X NoFix
(Load Task Register)
Instruction May Result in
System Hang
Under Certain Conditions LTR
X X NoFix
(Load Task Register)
Instruction May Result in
System Hang
Loading from Memory Type
X X NoFix
USWC (Uncacheable
Speculative Write Combine)
May Get Its Data Internally
Forwarded from a Previous
Pending Store
FXSAVE after FNINIT Without
X X NoFix
an Intervening FP (Floating
Point) Instruction May Save
Uninitialized Values for FDP
(x87 FPU Instruction Operand
(Data) Pointer Offset) and
FDS (x87 FPU Instruction
Operand (Data) Pointer
Selector)
FSTP (Floating Point
X X NoFix
Store) Instruction Under
Certain Conditions May Result
In Erroneously Setting a Valid
Bit on an FP (Floating
Point) Stack Register
Invalid Entries in Page-
X X NoFix
Directory-Pointer-Table
Register (PDPTR) May Cause
General Protection (#GP)
Exception if the Reserved Bits
are Set to One
Writing the Local Vector
Table (LVT)
X NoFix when an Interrupt is Pending
X
May Cause an Unexpected
Interrupt
The Processor May Report
X NoFix an Invalid TSS Fault Instead
X
of a #GP Fault
A Write to an APIC Register
X NoFix
X
Sometimes May Appear to
ERRATA
19