Intel SL3VS - Celeron 633 MHz Processor Specification page 52

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INTEL CELERON® PROCESSOR SPECIFICATION UPDATE
C39. Far Jump to New TSS With D-bit Cleared May Cause System
Hang
A task switch may be performed by executing a far jump through a task gate or to a new Task
Problem:
State Segment (TSS) directly. Normally, when such a jump to a new TSS occurs, the D-bit (which indicates
that the page referenced by a Page Table Entry (PTE) has been modified) for the PTE which maps the
location of the previous TSS will already be set and the processor will operate as expected. However, if the D-
bit is clear at the time of the jump to the new TSS, the processor will hang.
If an OS is used which can clear the D-bit for system pages, and which jumps to a new TSS on
Implication:
a task switch, then a condition may occur which results in a system hang. Intel has not identified any
commercial software which may encounter this condition; this erratum was discovered in a focused testing
environment.
Ensure that OS code does not clear the D-bit for system pages (including any pages that
Workaround:
contain a task gate or TSS). Use task gates rather than jumping to a new TSS when performing a task switch.
For the steppings affected see the Summary of Changes at the beginning of this section.
Status:
C40. Incorrect Chunk Ordering May Prevent Execution of the
Machine Check Exception Handler After BINIT#
If a catastrophic bus error is detected which results in a BINIT# assertion, and the BINIT#
Problem:
assertion is propagated to the processor's L2 cache at the same time that data is being sent to the processor,
then the data may become corrupted in the processor's L1 cache.
Since BINIT# assertion is due to a catastrophic event on the bus, the corrupted data will not be
Implication:
used. However, it may prevent the processor from executing the Machine Check Exception (MCE) handler,
causing the system to hang.
None identified
Workaround:
For the steppings affected see the Summary of Changes at the beginning of this section.
Status:
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