Intel SL3VS - Celeron 633 MHz Processor Specification page 71

C79. The instruction Fetch Unit (IFU) May Fetch Instructions
Based Upon Stale CR3 Data After a Write to CR3 Register
Problem: Under a complex set of conditions, there exists a one clock window following a write to the CR3
register where-in it is possible for the iTLB fill buffer to obtain a stale page translation based on the stale CR3
data. This stale translation will persist until the next write to the CR3 register, the next page fault or execution
of a certain class of instructions including RDTSC, CPUID, or IRETD with privilege level change.
Implication: The wrong page translation could be used leading to erroneous software behavior.
Workaround: Operating systems that are potentially affected can add a second write to the CR3 register.
Status: For the stepping affected see the Summary of Changes at the beginning of this section.
C80. The Processor Might not Exit Sleep State Properly Upon De-
assertion of CPUSLP# Signal
Problem: If the processor enters a sleep state upon assertion of CPUSLP# signal, and if the core to system
bus multiplier is an odd bus fraction, then the processor may not resume from the CPU sleep state upon the
de-assertion of CPUSLP# signal.
Implication: This erratum may result in a system hang during a resume from CPU sleep state.
Workaround: It is possible to workaround this in BIOS by not asserting CPUSLP# for power
management purposes.
Status: For the stepping affected see the Summary of Changes at the beginning of this section.
C81. During Boundary Scan, BCLK not Sampled High When SLP#
is Asserted Low
Problem: During boundary scan, BCLK is not sampled high when SLP# is asserted low.
Implication: Boundary scan results may be incorrect when SLP# is asserted low.
Workaround: Do not use boundary scan when SLP# is asserted low.
Status: For the steppings affected, see the Summary of Changes at the beginning of this section.
®
INTEL CELERON® PROCESSOR SPECIFICATION UPDATE
63