Intel SL3VS - Celeron 633 MHz Processor Specification page 40

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INTEL CELERON® PROCESSOR SPECIFICATION UPDATE
C15. Built-in Self Test Always Gives Nonzero Result
The Built-in Self Test (BIST) of the Celeron processor does not give a zero result to indicate a
Problem:
passing test. Regardless of pass or fail status, bit 6 of the BIST result in the EAX register after running BIST is
set.
Software which relies on a zero result to indicate a passing BIST will indicate BIST failure.
Implication:
Mask bit 6 of the BIST result register when analyzing BIST results.
Workaround:
For the steppings affected see the Summary of Changes at the beginning of this section.
Status:
C16. THERMTRIP# May Not Be Asserted as Specified
THERMTRIP# is a signal on the Celeron processor which is asserted when the core reaches a
Problem:
critical temperature during operation as detailed in the processor specification. The Celeron processor may
not assert THERMTRIP# until a much higher temperature than the one specified is reached.
The THERMTRIP# feature is not functional on the Celeron processor. Note that this erratum
Implication:
can only occur when the processor is running with a T
75° C.
Avoid operation of the Celeron processor outside of the thermal specifications defined by the
Workaround:
processor specifications.
For the steppings affected see the Summary of Changes at the beginning of this section.
Status:
C17. Cache State Corruption in the Presence of Page A/D-bit
Setting and Snoop Traffic
If an operating system uses the Page Access and/or Dirty bit feature implemented in the Intel
Problem:
architecture and there is a significant amount of snoop traffic on the bus, while the processor is setting the
Access and/or Dirty bit the processor may inappropriately change a single L1 cache line to the modified state.
The occurrence of this erratum may result in cache incoherency, which may cause parity
Implication:
errors, data corruption (with no parity error), unexpected application or operating system termination, or
system hangs.
It is possible for BIOS code to contain a workaround for this erratum.
Workaround:
For the steppings affected see the Summary of Changes at the beginning of this section.
Status:
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temperature over the maximum specification of
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