Intel SL3VS - Celeron 633 MHz Processor Specification page 90

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INTEL CELERON® PROCESSOR SPECIFICATION UPDATE
C7. EFLAGS Register Correction
The Intel Architecture Software Developer's Manual, Volume 1: Basic Architecture Section 3.7.2, Figure 3.7.
"EFLAGS Register" currently states:
Bit 11 "OF" as "X"
It should state:
Bit 11 "OF" as "S"
C8. PSE-36 Paging Mechanism
The Intel Architecture Software Developer's Manual, Vol 3: System Programming Guide Chapter 3, Section
3.9, third paragraph currently states:
As is shown in Table 3-3, the following flags must be set or cleared to enable the PSE-36 paging
mechanism:
•
PSE-36 CPUID feature flag-When set, it indicates the availability of the PSE-36 paging
mechanism on the IA-32 processor on which the CPUID instruction is executed.
•
PG flag (bit 31) in register CR0-Set to 1 to enable paging.
•
PSE flag (bit 4) in control register CR4 - Set to 1 to enable the page size extension for 4-
Mbyte pages.
•
PAE flag (bit 5) in control register CR4-Clear to 0 to disable the PAE paging mechanism.
It should state:
As is shown in Table 3-3, the following flags must be set or cleared to enable the PSE-36 paging
mechanism:
•
PSE-36 CPUID feature flag-When set, it indicates the availability of the PSE-36 paging
mechanism on the IA-32 processor on which the CPUID instruction is executed.
•
PG flag (bit 31) in register CR0-Set to 1 to enable paging.
•
PAE flag (bit 5) in control register CR4-Clear to 0 to disable the PAE paging mechanism.
•
PSE flag (bit 4) in control register CR4 and the PS flag in PDE- Set to 1 to enable the
page size extension for 4-Mbyte pages.
•
Or the PSE flag (bit 4) in control register CR4- Set to 1 and the PS flag (bit 7) in PDE- Set
to 0 to enable 4-KByte pages with 32-bit addressing (below 4GBytes).
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