Intel SL3VS - Celeron 633 MHz Processor Specification page 78

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INTEL CELERON® PROCESSOR SPECIFICATION UPDATE
Status: For the steppings affected, see the Summary Tables of Changes.
C92. Page with PAT (Page Attribute Table) Set to USWC
(Uncacheable Speculative Write Combine) While Associated
MTRR (Memory Type Range Register) is UC (Uncacheable)
May Consolidate to UC
Problem:
For a page whose PAT memory type is USWC while the relevant MTRR
memory type is UC, the consolidated memory type may be treated as UC (rather
than WC as specified in IA-32 Intel® Architecture Software Developer's
Manual)..
Implication: When this erratum occurs, the memory page may be treated as UC (rather than
WC). This may have a negative performance impact.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.
C93. Under Certain Conditions LTR (Load Task Register)
Instruction May Result in System Hang
Problem: An LTR instruction may result in a system hang if all the following conditions
are met:
1. Invalid data selector of the TR (Task Register) resulting with either #GP (General
Protection Fault) or #NP (Segment Not Present Fault).
2. GDT (Global Descriptor Table) is not 8-bytes aligned.
3. Data BP (breakpoint) is set on cache line containing the descriptor data..
Implication: This erratum may result in system hang if all conditions have been met. This
erratum has not been observed in commercial operating systems or
software. For performance reasons, GDT is typically aligned to 8-bytes.
Workaround: Software should align GDT to 8-bytes
Status:
For the steppings affected, see the Summary Tables of Changes.
C94. Loading from Memory Type USWC (Uncacheable Speculative
Write Combine) May Get Its Data Internally Forwarded from a
Previous Pending Store
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