Intel SL3VS - Celeron 633 MHz Processor Specification page 45

There are two possible workarounds for this erratum:
Workaround:
1. Rather than using the MOVSX-MOVD or CBW-MOVD pairing to handle one variable at a time, use the
sign extension capabilities (PSRAW, etc.) within MMX technology for operating on multiple variables. This
would result in higher performance as well.
2. Insert another operation that modifies or copies the sign-extended value between the MOVSX/IMUL/CBW
instruction and the MOVD instruction as in the example below:
XOR EAX, EAX (or SUB EAX, EAX)
MOVSX AX, BL (or other MOVSX, other IMUL or CBW instruction)
*MOV EAX, EAX
MOVD MM0, EAX
*Note: MOV EAX, EAX is used here as it is fairly generic. Again, EAX can be any 32-bit register.
For the steppings affected see the Summary of Changes at the beginning of this section.
Status:
C24. Premature Execution of a Load Operation Prior to Exception
Handler Invocation
This erratum can occur with any of the following situations:
Problem:
1. If an instruction that performs a memory load causes a code segment limit violation
2. If a waiting floating-point instruction or MMX™ instruction that performs a memory load has a floating-
point exception pending
3. If an MMX instruction that performs a memory load and has either CR0.EM =1 (Emulation bit set), or a
floating-point Top-of-Stack (FP TOS) not equal to 0, or a DNA exception pending
If any of the above circumstances occur, it is possible that the load portion of the instruction will have
executed before the exception handler is entered.
In normal code execution where the target of the load operation is to write back memory there
Implication:
is no impact from the load being prematurely executed, nor from the restart and subsequent re-execution of
that instruction by the exception handler. If the target of the load is to uncached memory that has a system
side effect, restarting the instruction may cause unexpected system behavior due to the repetition of the side
effect.
Code which performs loads from memory that has side-effects can effectively workaround this
Workaround:
behavior by using simple integer-based load instructions when accessing side-effect memory and by ensuring
that all code is written such that a code segment limit violation cannot occur as a part of reading from side-
effect memory.
For the steppings affected see the Summary of Changes at the beginning of this section.
Status:
®
INTEL CELERON® PROCESSOR SPECIFICATION UPDATE
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