Intel SL3VS - Celeron 633 MHz Processor Specification page 38

®
INTEL CELERON® PROCESSOR SPECIFICATION UPDATE
C11. Potential Early Deassertion of LOCK# During Split-Lock
Cycles
During a split-lock cycle there are four bus transactions: 1st ADS# (a partial read), 2nd ADS# (a
Problem:
partial read), 3rd ADS# (a partial write), and the 4th ADS# (a partial write). Due to this erratum, LOCK# may
deassert one clock after the 4th ADS# of the split-lock cycle instead of after the 4th RS# assertion
corresponding to the 4th ADS# has been sampled. The following sequence of events are required for this
erratum to occur:
1. A lock cycle occurs (split or nonsplit).
2. Five more bus transactions (assertion of ADS#) occur.
3. A split-lock cycle occurs and BNR# toggles after the 3rd ADS# (partial write) of the split-lock cycle. This in
turn delays the assertion of the 4th ADS# of the split-lock cycle. BNR# toggling at this time could most
likely happen when the bus is set for an IOQ depth of 2.
When all of these events occur, LOCK# will be deasserted in the next clock after the 4th ADS# of the split-lock
cycle.
This may affect chipset logic which monitors the behavior of LOCK# deassertion.
Implication:
None identified
Workaround:
For the steppings affected see the Summary of Changes at the beginning of this section.
Status:
C12. A20M# May Be Inverted After Returning From SMM and
Reset
This erratum is seen when software causes the following events to occur:
Problem:
1. The assertion of A20M# in real address mode.
2. After entering the 1-Mbyte address wrap-around mode caused by the assertion of A20M#, there is an
assertion of SMI# intended to cause a Reset or remove power to the processor. Once in the SMM
handler, software saves the SMM state save map to an area of nonvolatile memory from which it can be
restored at some point in the future. Then software asserts RESET# or removes power to the processor.
3.
After exiting Reset or completion of power-on, software asserts SMI# again. Once in the SMM handler, it
then retrieves the old SMM state save map which was saved in event 2 above and copies it into the
current SMM state save map. Software then asserts A20M# and executes the RSM instruction. After
exiting the SMM handler, the polarity of A20M# is inverted.
If this erratum occurs, A20M# will behave with a polarity opposite from what is expected (i.e.,
Implication:
the 1-Mbyte address wrap-around mode is enabled when A20M# is deasserted, and does not occur when
A20M# is asserted).
Software should save the A20M# signal state in nonvolatile memory before an assertion of
Workaround:
RESET# or a power down condition. After coming out of Reset or at power on, SMI# should be asserted
again. During the restoration of the old SMM state save map described in event 3 above, the entire map
should be restored, except for bit 5 of the byte at offset 7F18h. This bit should retain the value assigned to it
when the SMM state save map was created in event 3. The SMM handler should then restore the original
value of the A20M# signal.
30