Intel SL3VS - Celeron 633 MHz Processor Specification page 86

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INTEL CELERON® PROCESSOR SPECIFICATION UPDATE
C111 Performance Monitoring Event FP_MMX_TRANS_TO_MMX
May Not Count Some Transitions
Performance Monitor Event FP_MMX_TRANS_TO_MMX (Event CCH, Umask 01H)
Problem:
counts transitions from x87 Floating Point (FP) to MMX™ instructions. Due to this erratum, if
only a small number of MMX instructions (including EMMS) are executed immediately after the
last FP instruction, an FP to MMX transition may not be counted.
The count value for Performance Monitoring Event FP_MMX_TRANS_TO_MMX
Implication:
may be lower than expected. The degree of undercounting is dependent on the occurrences of the
erratum condition while the counter is active. Intel has not observed this erratum with any
commercially available software.
None identified.
Workaround:
For the steppings affected see the Summary of Changes at the beginning of this section.
Status:
78