Intel SL3VS - Celeron 633 MHz Processor Specification page 102

®
INTEL CELERON® PROCESSOR SPECIFICATION UPDATE
IF CPU supports MCE
THEN
IF CPU supports MCA
THEN
IF IA32_ MCG_CAP.MCG_CTL_P = 1
(* IA32_MCG_CTL register is present *)
IA32_MCG_CTL FFFFFFFFFFFFFFFFH;
(* enables all MCA features *)
FI;
COUNT <-- IA32_MCG_CAP.Count;
MAX_BANK_NUMBER <-- COUNT  1;
(* determine number of error-reporting banks supported *)
IF (P6 Family Processor)
THEN
FOR error-reporting banks (1 through MAX_BANK_NUMBER) DO
OD
ELSE (* Pentium 4 and Intel Xeon Processors *)
FOR error-reporting banks (0 through MAX_BANK_NUMBER) DO
OD
FI;
FOR error-reporting banks (0 through MAX_BANK_NUMBER) DO
IA32_MC i _STATUS <-- 0000000000000000H; (* clears all errors *)
OD
FI;
Set the MCE flag (bit 6) in CR4 register to enable machine-check exceptions;
FI;
It should state:
14.5 MACHINE-CHECK INITIALIZATION
To use the processors machine-check architecture, software must initialize the processor to activate the
machine-check exception and the error-reporting mechanism.
Example gives pseudocode for performing this initialization. This pseudocode checks for the existence of the
machine-check architecture and exception on the processor, then enables the machine-check exception and
the error-reporting register banks. The pseudocode shown is compatible with the Pentium 4, Intel Xeon, P6
family, and Pentium processors.
Following power up or power cycling, the IA32_MC i _STATUS registers are not guaranteed to have valid data
until after the registers are initially cleared to all 0s by software, as shown in the initialization pseudocode in
94
IA32_MC i _CTL <-- FFFFFFFFFFFFFFFFH;
(* enables logging of all errors except for MC0_CTL register *)
IA32_MC i _CTL <-- FFFFFFFFFFFFFFFFH;
(* enables logging of all errors including MC0_CTL register *)