Intel SL3VS - Celeron 633 MHz Processor Specification page 72

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INTEL CELERON® PROCESSOR SPECIFICATION UPDATE
C82. Incorrect Assertion of THERMTRIP# Signal
Problem: The internal control register bit responsible for operation of the Thermtrip circuit functionality may
power up in a non-initialized state. As a result, THERMTRIP# may be incorrectly asserted during de-assertion
of RESET# at nominal operating temperatures. When THERMTRIP# is asserted as a result of this erratum,
the processor may shut down internally and stop execution but in few cases continue to execute.
Implication: This issue can lead to intermittent system power-on boot failures. The occurrence and
repeatability of failures is system dependent, however all systems and processors are susceptible to failure.
In addition, the processor may fail to stop execution during the event of a valid THERMTRIP# assertion
resulting in the potential for permanent processor damage.
Workaround: To prevent the risk of power-on boot failures or catastrophic thermal failures, a platform
workaround is required. The system must provide a rising edge on the TCK signal during the power-on
sequence that meets all of the following requirements:
· Rising edge occurs after Vcc_core is valid and stable
· Rising edge occurs before or at the de-assertion of RESET#
· Rising edge occurs after all Vref input signals are at valid voltage levels
· TCK input meets the Vih min and max spec as mentioned In EMTS
Specific workaround implementations may be platform specific. The following examples have been tested as
acceptable workaround implementations.
Please note, the example workaround circuits attached require circuit modification for ITP tools to function
correctly. These modifications must remove the workaround circuitry from the platform and may cause
systems to fail to boot. Review the accompanying notes with each workaround for ITP modification details. If
the system fails to boot when using ITP, issuing the ITP 'Reset Target' command on failing systems will reset
the system and provide a sufficient rising edge on the TCK pin to ensure proper system boot.
In addition, the example workaround circuits shown do not support production motherboard test
methodologies that require the use of the processor JTAG/TAP port. Alternative workaround solutions must
be found if such test capability is required.
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