Intel SL3VS - Celeron 633 MHz Processor Specification page 85

C108: INVLPG Operation for Large (2M/4M) Pages May be
Incomplete under Certain Conditions
The INVLPG instruction may not completely invalidate Translation Look-aside Buffer
Problem:
(TLB) entries for large pages (2M/4M) when both of the following conditions exist:
•
Address range of the page being invalidated spans several Memory Type Range
Registers (MTRRs) with different memory types specified
•
INVLPG operation is preceded by a Page Assist Event (Page Fault (#PF) or an
access that results in either A or D bits being set in a Page Table Entry (PTE))
Stale translations may remain valid in TLB after a PTE update resulting in unpredictable
Implication:
system behavior. Intel has not observed this erratum with any commercially available
software.
Software should ensure that the memory type specified in the MTRRs is the same for the
Workaround:
entire address range of the large page.
For the steppings affected see the Summary of Changes at the beginning of this
Status:
section.
C109: Page Access Bit May be Set Prior to Signaling a Code
Segment Limit Fault
Problem : If code segment limit is set close to the end of a code page, then due to this erratum the
memory page Access bit (A bit) may be set for the subsequent page prior to general
protection fault on code segment limit.
Implication : When this erratum occurs, a non-accessed page which is present in memory and follows
a page that contains the code segment limit may be tagged as accessed.
Workaround : Erratum can be avoided by placing a guard page (non-present or non-executable
page) as the last page of the segment or after the page that includes the code segment
limit.
For the steppings affected see the Summary of Changes at the beginning of this section.
Status:
C110: EFLAGS, CR0, CR4 and the EXF4 Signal May be Incorrect
after Shutdown
When the processor is going into shutdown due to an RSM inconsistency failure,
Problem:
EFLAGS, CR0 and CR4 may be incorrect. In addition the EXF4 signal may still be
asserted. This may be observed if the processor is taken out of shutdown by NMI#.
A processor that has been taken out of shutdown may have an incorrect EFLAGS, CR0
Implication:
and CR4. In addition the EXF4 signal may still be asserted.
None identified.
Workaround:
For the steppings affected see the Summary Table of Changes
Status:
®
INTEL CELERON® PROCESSOR SPECIFICATION UPDATE
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